Hitachi H8/500 Series - Operation; Watchdog Timer Mode; Read Addresses of TCNT and TCSR

Coding Examples:
To clear TCNT to 00: MOV.W #H'5A00, @H'FFEC
To write H'4F in TCSR: MOV.W #H'A54F, @H'FFEC
2. Reading TCNT and TCSR: The read addresses are H'FFEC for TCSR and H'FFED for
TCNT, as indicated in table 13-2.
These two registers are read like other registers. Byte access instructions can be used.
Table 13-2 Read Addresses of TCNT and TCSR
Read Address Register
H'FFEC TCSR
H'FFED TCNT
13.3 Operation
13.3.1 Watchdog Timer Mode
The watchdog timer function begins operating when software sets the WT/IT and TME bits to 1 in
the TCSR. Thereafter, software should periodically rewrite the contents of the timer counter
(normally by writing H'00) to prevent the count from overflowing. If a program crash allows the
timer count to overflow, the watchdog timer requests a nonmaskable interrupt (NMI) as shown in
figure 13-3.
NMI requests from the watchdog timer have the same vector as NMI requests from the NMI pin,
so the NMI interrupt-handling routine must check the OVF bit in the TCSR to determine the
source of the interrupt.
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