Hitachi H8/500 Series - Interrupt Sequence (Minimum Mode, On-Chip Memory)

(3)
Vector address
SP - 4
SP - 2
(4)VectorSRPC(2)(2)(2)
(1)(1)(1)
NMI, IRQ0 IRQ1 ø Interrupt address bus Interrupt data bus (16 bits) Interrupt reset signal Interrupt write signal
Priority level decision and wait for end of current instruction
Stack accessInternal
process- ing cycle
Prefetch first instruction of interrupt- handling routine
Start instruction execution
Interrupt accepted
(1) Instruction prefetch address (2) Instruction code (3) Starting address of interrupt-handling routine (4) First instruction of interrupt-handling routine Note: This timing chart applies to the minimum mode when the program and stack areas are both in on-chip memory and the interrupt-handling routine starts
at an even address.
Figure 5-4 Interrupt Sequence (Minimum Mode, On-Chip Memory)
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