Hitachi H8/500 Series - Reset During Memory Access (Mode 3)

Masked-ROM Version
A to A19 0
RES
P1 / ø*
0
Internal reset signal
R/W
AS, RD and DS (read)
WR and DS (write)
D to D (write)70
I/O ports
High impedance
H’0000
External memory access
T
1 T2
High impedance
*
The dotted line indicates that P10/ø is an input port if the corresponding DDR bit is 0,
but a clock output pin if the DDR bit is 1.
Figure E-6 Reset during Memory Access (Mode 3)
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