15.2.2 A/D Control/Status Register (ADCSR)—H'FFE8
* Software can write a 0 in bit 7 to clear the flag, but cannot write a 1 in this bit.
The A/D control/status register (ADCSR) is an 8-bit readable/writable register that controls the
operation of the A/D converter module.
The ADCSR is initialized to H'00 at a reset and in the standby modes.
Bit 7—A/D End Flag (ADF): This status flag indicates the end of one cycle of A/D conversion.
Bit 7
ADF Description
0 This bit is cleared from 1 to 0 when: (Initial value)
1. The chip is reset or placed in a standby mode.
2. The CPU reads the ADF bit, then writes a “0” in this bit.
3. An A/D interrupt is served by the data transfer controller (DTC).
1 This bit is set to 1 at the following times:
1. Single mode: when one A/D conversion is completed.
2. Scan mode: when inputs on all selected channels have been converted.
Bit 6—A/D Interrupt Enable (ADIE): This bit selects whether to request an A/D interrupt
(ADI) when A/D conversion is completed.
Bit 6
ADIE Description
0 The A/D interrupt request (ADI) is disabled. (Initial value)
1 The A/D interrupt request (ADI) is enabled.
Bit 76543210
ADF ADIE ADST SCAN CKS CH2 CH1 CH0
Initial value 00000000
Read/Write R/(W)* R/W R/W R/W R/W R/W R/W R/W
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