Hitachi H8/500 Series - Register Descriptions; Free-Running Counter (FRC)-HFF92, HFFA2, HFFB2

Table 10-2 Register Configuration (cont)
Initial
Channel Name Abbreviation R/W Value Address
Timer control register TCR R/W H'00 H'FFB0
Timer control/status register TCSR R/(W)* H'00 H'FFB1
Free-running counter (High) FRC (H) R/W H'00 H'FFB2
Free-running counter (Low) FRC (L) R/W H'00 H'FFB3
3 Output compare register A (High) OCRA (H) R/W H'FF H'FFB4
Output compare register A (Low) OCRA (L) R/W H'FF H'FFB5
Output compare register B (High) OCRB (H) R/W H'FF H'FFB6
Output compare register B (Low) OCRB (L) R/W H'FF H'FFB7
Input capture register (High) ICR (H) R H'00 H'FFB8
Input capture register (Low) ICR (L) R H'00 H'FFB9
* Software can write a “0” to clear bits 7 to 4, but cannot write a “1” in these bits.
10.2 Register Descriptions
10.2.1 Free-Running Counter (FRC)—H'FF92, H'FFA2, H'FFB2
Each FRC is a 16-bit readable/writable up-counter that increments on an internal pulse generated
from a clock source. The clock source is selected by the clock select 1 and 0 bits (CKS1 and
CKS0) of the timer control register (TCR).
The FRC can be cleared by compare-match A.
When the FRC overflows from H'FFFF to H'0000, the overflow flag (OVF) in the timer
control/status register (TCSR) is set to “1.”
Because the FRC is a 16-bit register, a temporary register (TEMP) is used when the FRC is
written or read. See section 10.3, “CPU Interface” for details.
The FRCs are initialized to H'0000 at a reset and in the standby modes.
Bit 1514131211109876543210
Initial value 0000000000000000
Read/WriteR/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
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