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Hitachi H8/500 Series

Hitachi H8/500 Series
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SYSCR1—System Control Register 1 H'FEFC Port 1
Bit 76543210
IRQ
1E IRQ0E NMIEG BRLE
Initial value 10000111
Read/Write R/W R/W R/W R/W
Nonmaskable Interrupt Edge
0 An NMI request is generated on the falling edge of the NMI pin input.
1 An NMI request is generated on the rising edge of the NMI pin input.
Bus Release Enable
0P1
2 and P13 are I/O ports.
1P1
2 is the BACK output pin. P13 is the BREQ input pin.
Register name
Name of the on-chip
supporting module
Names of the
bits.
Dashes (—)
indicate
reserved bits.
Address to which the
register is mapped
Acronym of the register
Bit
numbers
Initial bit
values
Full name of the bit
Functions of the bit settings
Interrupt Request 0 Enable
0P1
5 is an I/O port; IRQ0 input is disabled.
1P1
5 is the IRQ0 input pin.
Interrupt Request 1 Enable
0P1
6 is an I/O port; IRQ1 input is disabled.
1P1
6 is the IRQ1 input pin.
Type of access permitted
R Read only
W Write only
R/W Both read and write
B.2 Register Descriptions
372
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