10.1.4 Register Configuration
Table 10-2 lists the registers of each free-running timer channel.
Table 10-2 Register Configuration
Initial
Channel Name Abbreviation R/W Value Address
Timer control register TCR R/W H'00 H'FF90
Timer control/status register TCSR R/(W)* H'00 H'FF91
Free-running counter (High) FRC (H) R/W H'00 H'FF92
Free-running counter (Low) FRC (L) R/W H'00 H'FF93
1 Output compare register A (High) OCRA (H) R/W H'FF H'FF94
Output compare register A (Low) OCRA (L) R/W H'FF H'FF95
Output compare register B (High) OCRB (H) R/W H'FF H'FF96
Output compare register B (Low) OCRB (L) R/W H'FF H'FF97
Input capture register (High) ICR (H) R H'00 H'FF98
Input capture register (Low) ICR (L) R H'00 H'FF99
Timer control register TCR R/W H'00 H'FFA0
Timer control/status register TCSR R/(W)* H'00 H'FFA1
Free-running counter (High) FRC (H) R/W H'00 H'FFA2
Free-running counter (Low) FRC (L) R/W H'00 H'FFA3
2 Output compare register A (High) OCRA (H) R/W H'FF H'FFA4
Output compare register A (Low) OCRA (L) R/W H'FF H'FFA5
Output compare register B (High) OCRB (H) R/W H'FF H'FFA6
Output compare register B (Low) OCRB (L) R/W H'FF H'FFA7
Input capture register (High) ICR (H) R H'00 H'FFA8
Input capture register (Low) ICR (L) R H'00 H'FFA9
* Software can write a “0” to clear bits 7 to 4, but cannot write a “1” in these bits.
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