Hitachi H8/500 Series - Tables of Instruction Execution Cycles

A.4.2 Tables of Instruction Execution Cycles
Tables A-7 (1) through (6) should be read as shown below:
J + K: Number of
instruction fetch cycles.
Instruction
Rn @Rn @(d:8, Rn) @(d:16, Rn) @–Rn @Rn+ @aa:8 @aa:16 #xx:8 #xx:16
Addressing mode
ADD.B
ADD.W
ADD:Q.B
ADD:Q.W
DADD
1 1 25565
6
563
1
J
11231
1
232
K
3
2 1 25565
6
56 4
2 1 27787
8
78
4 1 27787
8
78
2
I: Total number of bytes
written and read when
operand is in memory.
Shading in the I column means
the operand cannot be in memory.
Shading indicates addressing modes
that cannot be used with this instruction.
4
359
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