Size CCR Bit
Mnemonic Operation B/W N Z V C
Data MOV: G (EAs) → Rd B/W ↕↕0—
transfer Rs → (EAd)
#IMM → (EAd)
MOV: E #IMM → Rd (short format) B ↕↕0—
MOV: F @ (d: 8, FP) → Rd B/W ↕↕0—
Rs → @ (d: 8, FP)(short format)
MOV: I #IMM → Rd (short format) W ↕↕0—
MOV: L (@aa: 8) → Rd (short format) B/W ↕↕0—
MOV: S Rs → (@aa: 8) (short format) B/W ↕↕0—
LDM @ SP + → Rn (register list) W — — — —
STM Rn (register list) → @ – SP W — — — —
XCH Rs ←→ Rd W — — — —
SWAP Rd (upper byte) ←→ Rd (lower byte) B ↕↕0—
MOVTPE Rs → (EAd) Synchronized with E clock B — — — —
MOVFPE (EAs) → Rd Synchronized with E clock B — — — —
Arith- ADD: G Rd + (EAs) → Rd B/W ↕↕↕↕
metic ADD: Q (EAd) + #IMM → (EAd) B/W ↕↕↕↕
opera- (#IMM = ±1, ±2) (short format)
tions ADDS Rd + (EAs) → Rd B/W — — — —
(Rd is always word size)
ADDX Rd + (EAs) + C → Rd B/W ↕↕↕↕
DADD (Rd)10 + (Rs)10 + C → (Rd)10 B—↕ — ↕
SUB Rd – (EAs) → Rd B/W ↕↕↕↕
SUBS Rd – (EAs) → Rd B/W — — — —
SUBX Rd – (EAs) – C → Rd B/W ↕↕↕↕
DSUB (Rd)10 – (Rs)10 – C → (Rd)10 B—↕ — ↕
MULXU Rd × (EAs) → Rd 8 × 8 B/W ↕↕00
(Unsigned) 16 × 16
DIVXU Rd ÷ (EAs) → Rd 16 ÷ 8 B/W ↕↕↕0
(Unsigned) 32 ÷ 16
CMP: G Rd – (EAs), Set CCR B/W ↕↕↕↕
(EAd) – #IMM, Set CCR
CMP: E Rd – #IMM, Set CCR (short format) B ↕↕↕↕
CMP: I Rd – #IMM, Set CCR (short format) W ↕↕↕↕
338
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