Coding Examples:
To select the rising edge of the NMI input: BSET.B #4, @H'FFFC
To select the falling edge of the NMI input: BCLR.B #4, @H'FFFC
IRQ0 (Interrupt Request 0): An IRQ0 interrupt can be requested by a Low input to the IRQ0 pin
and/or a watchdog timer overflow. A Low IRQ0 input requests an IRQ0 interrupt if the interrupt
request enable 0 bit (IRQ0E) in the P1CR is set to “1.” IRQ0 must be held Low until the CPU
accepts the interrupt. Otherwise the request will be ignored. A watchdog timer overflow requests
an IRQ0 interrupt if the TME bit is set to “1” and the WT/IT bit is cleared to “0” in the watchdog
timer's control/status register. See section 13, “Watchdog Timer” for details of the watchdog
timer.
The IRQ0 interrupt can be assigned any priority level from 7 to 0 by setting the corresponding
value in the upper four bits of IPRA. If bit 4 of data transfer enable register A (DTEA) is set to
“1,” an IRQ0 interrupt starts the data transfer controller. Otherwise the interrupt is served by the
CPU.
In the CPU interrupt-handling sequence for IRQ0, the T bit of the status register is cleared to “0,”
and the interrupt mask level is set to the value in the upper four bits of IPRA.
Coding Examples:
To enable IRQ0 to be requested by IRQ0 input: BSET.B #5, @H'FFFC
To assign priority level 7 to IRQ0: OR.B #70, @H'FFF0
To have IRQ0 start the DTC: BSET.B #4, @H'FFF4
IRQ1 (Interrupt Request 1): An IRQ0 interrupt is requested by a High-to-Low transition at the
IRQ1 pin. The IRQ1 interrupt is enabled only when the interrupt request enable 1 bit (IRQ1E) in
the P1CR is set to “1.”
The IRQ1 interrupt can be assigned any priority level from 7 (high) to 0 (low) by setting the
corresponding value in the lower four bits of IPRA. If bit 0 of data transfer enable register A
(DTEA) is set to “1,” an IRQ1 interrupt starts the data transfer controller. Otherwise the interrupt
is served by the CPU.
The interrupt controller holds the IRQ1 request until the IRQ1 exception-handling sequence
begins, then clears the IRQ1 request. If another interrupt is requested at the IRQ1 pin during the
IRQ1 interrupt-handling routine, the request is held, but the IRQ1 exception-handling sequence is
not carried out immediately because the interrupt is masked by bits I2 to I0 in the status register.
On return from the interrupt-handling routine one more instruction is executed, then the
exception-handling sequence for the second IRQ1 interrupt is carried out.
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