P1CR selects the functions of four of the port 1 pins. It also selects the input edge of the NMI pin.
At a reset and in the hardware standby mode, P1CR is initialized to H'87. It is not initialized in
the software standby mode.
Bit 7—Reserved: This bit cannot be modified and is always read as “1.”
Bit 6—Interrupt Request 1 Enable (IRQ1E): This bit selects the function of pin P16.
Bit 6
IRQ
1E Description
0P1
6 functions as an input/output pin. (Initial value)
1P1
6 functions as the IRQ1 input pin, regardless of the value set in P16DDR. (However,
the CPU can still read the pin status by reading P1DR.)
Bit 5—Interrupt Request 0 Enable (IRQ0E): This bit selects the function of pin P15.
Bit 5
IRQ
0E Description
0P1
5 functions as an input/output pin. (Initial value)
1P1
5 functions as the IRQ0 input pin, regardless of the value set in P15DDR. (However,
the CPU can still read the pin status by reading P1DR.)
Bit 4—Nonmaskable Interrupt Edge (NMIEG): This bit selects the input edge of the NMI pin.
It is not related to port 0.
Bit 4
NMIEG Description
0 A nonmaskable interrupt is generated on the falling edge (Initial value)
of the input at the NMI pin.
1 A nonmaskable interrupt is generated on the rising edge
of the input at the NMI pin.
Bit 3—Bus Release Enable (BRLE): This bit selects the functions of pins P12 and P13. It is
valid only in the expanded modes (modes 1, 2, 3, and 4). In the single-chip mode, pins P12 and
P13 function as input/output pins regardless of the value of the BRLE bit.
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