Hitachi H8/500 Series - Page 179

162
A: Before Execution of BSET Instruction
P5
7
P5
6
P5
5
P5
4
P5
3
P5
2
P5
1
P5
0
Input/output Input Input Output Output Output Output Output Output
Pin state Low High Low Low Low Low Low Low
DDR 0 0 1 1 1 1 1 1
DR 10000000
Pull-up On Off Off Off Off Off Off Off
B: Execution of BSET Instruction
BSET.B #0 @PORT5 ;set bit 0 in data register
C: After Execution of BSET Instruction
P5
7
P5
6
P5
5
P5
4
P5
3
P5
2
P5
1
P5
0
Input/output Input Input Output Output Output Output Output Output
Pin state Low High Low Low Low Low Low High
DDR 0 0 1 1 1 1 1 1
DR 01000001
Pull-up Off On Off Off Off Off Off Off
Explanation: To execute the BSET instruction, the CPU begins by reading port 5. Since P57 and
P56 are input pins, the CPU reads the level of these pins directly, not the value in the data register.
It reads P57 as low (0) and P56 as high (1).
Since P55 to P50 are output pins, for these pins the CPU reads the value in the data register (0).
The CPU therefore reads the value of port 5 as H'40, although the actual value in P5DR is H'80.
Next the CPU sets bit 0 of the read data to 1, changing the value to H'41.
Finally, the CPU writes this value (H'41) back to P5DR to complete the BSET instruction.
As a result, bit P50 is set to 1, switching pin P50 to high output. In addition, bits P57 and P56 are
both modified, changing the on/off settings of the MOS pull-up transistors of pins P57 and P56.
Programming Solution: The switching of the pull-ups for P57 and P56 in the preceding example
can be avoided by using a byte in RAM as a work area for P5DR, performing bit manipulations on
the work area, then writing the result to P5DR.
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