Hitachi H8/500 Series - Page 206

< Lower byte write >
CPU wites
data H’55
Bus interface
TEMP
[H’AA]
FRCH
[H’AA]
FRCL
[H’55]
Module data bus
< Upper byte write >
CPU wites
data H’AA
Bus interface
TEMP
[H’AA]
FRCH
[ ]
FRCL
[ ]
Module data bus
Figure 10-2 (a) Write Access to FRC (When CPU Writes H'AA55)
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