Bit 7
CMFB Description
0 This bit is cleared from 1 to 0 when: (Initial value)
1. The CPU reads the CMFB bit, then writes a “0” in this bit.
2. Compare-match interrupt B is served by the data transfer controller (DTC).
1 This bit is set to 1 when TCNT = TCORB.
Bit 6—Compare-Match Flag A (CMFA): This status flag is set to “1” when the timer count
matches the time constant set in TCORA.
Bit 6
CMFA Description
0 This bit is cleared from 1 to 0 when: (Initial value)
1. The CPU reads the CMFA bit, then writes a “0” in this bit.
2. Compare-match interrupt A is served by the data transfer controller (DTC).
1 This bit is set to 1 when TCNT = TCORA.
Bit 5—Timer Overflow Flag (OVF): This status flag is set to “1” when the timer count
overflows (changes from H'FF to H'00).
Bit 5
OVF Description
0 This bit is cleared from 1 to 0 when the CPU reads (Initial value)
the OVF bit, then writes a “0” in this bit.
1 This bit is set to 1 when TCNT changes from H'FF to H'00.
Bit 4—Reserved: This bit cannot be modified and is always read as “1.”
Bits 3 to 0—Output Select 3 to 0 (OS3 to OS0): These bits specify the effect of compare-match
events on the timer output signal (TMO). Bits OS3 and OS2 control the effect of compare-match B
on the output level. Bits OS1 and OS0 control the effect of compare-match A on the output level.
When all four output select bits are cleared to “0” the TMO signal is not output. The TMO output
is “0” before the first compare-match.
Bit 3 Bit 2
OS3 OS2 Description
0 0 No change when compare-match B occurs. (Initial value)
0 1 Output changes to “0” when compare-match B occurs.
1 0 Output changes to “1” when compare-match B occurs.
1 1 Output inverts (toggles) when compare-match B occurs.
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