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Hitachi H8/500 Series - Page 24

Hitachi H8/500 Series
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Table 1-1 Features (cont)
Feature Description
Serial com- • Asynchronous or synchronous mode (selectable)
munication • Full duplex: can send and receive simultaneously
interface (SCI) • Built-in baud rate generator
A/D converter • 10-Bit resolution
• 8 channels, controllable in single mode or scan mode (selectable)
• Sample-and-hold function
I/O ports • 57 Input/output pins (six 8-bit ports, one 5-bit port, one 4-bit port)
• 8 Input-only pins (one 8-bit port)
• Memory-mapped I/O
Interrupt • 3 external interrupt pins (NMI, IRQ
0, IRQ1)
controller • 19 internal interrupts
(INTC) • 8 priority levels
Data transfer Performs bidirectional data transfer between memory and I/O independently
controller (DTC) of the CPU
Wait-state Can insert wait states in access to external memory or I/O
controller (WSC)
Operating 5 MCU operating modes
modes • Expanded minimum modes, supporting up to 64k bytes external memory
with or without using on-chip ROM (Modes 1 and 2)
• Expanded maximum modes, supporting up to 1M byte external memory
with or without using on-chip ROM (Modes 3 and 4)
• Single-chip mode (Mode 7)
3 power-down modes
• Sleep mode
• Software standby mode
• Hardware standby mode
Other features • E clock output available
• Clock generator on-chip
Model Name Package Options ROM
HD6475328CG 84-Pin windowed LCC (CG-84) PROM
HD6475328CP 84-Pin PLCC (CP-84)
HD6475328F 80-Pin QFP (FP-80A)
HD6435328CP 84-Pin PLCC (CP-84) Mask
HD6435328F 80-Pin QFP (FP-80A) ROM
3
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