2. Mode 2
Figures E-3 and E-4 show how the pin states change when the RES pin goes Low during external
memory access in mode 2.
As soon as RES goes Low, all ports are initialized to the input (high-impedance) state. The AS,
DS, RD, and WR signals all go High. The data bus (D7 to D0) is placed in the high-impedance
state. Pins P57/A15 to P50/A8 of the address bus are initialized as input ports.
Pins A7 to A0 of the address bus and the R/W signal are initialized 1.5 ø clock periods after the
Low state of the RES pin is sampled. Pins A7 to A0 are made Low. The signal is made High.
The clock output pins P10/ø and P11/E are initialized 0.5 ø clock periods after the Low state of the
RES pin is sampled. Both pins are initialized to the output state.
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