Hitachi H8/500 Series - Page 48

Figure 2-2 is a map of page 0 of the address space.
On-chip RAM (when enabled)
H'0000
Exception vector table
DTC vector table
H'7FFF
H'8000
H'FB80
H'FF80
H'FFFF
On-chip register field
On-chip ROM
(modes 2, 4, and 7)
or external memory
(modes 1 and 3)
Figure 2-2 Map of Page 0
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