Intel MCS 51

HARDWARE DESCRIPTION OF THE 8XC51FX
CONTENTS PAGE
1.0 INTRODUCTION .................................. 5-3
2.0 MEMORY..............................................5-3
2.1 Program Memory............................. 5-3
2.2 Data Memory ................................... 5-3
3.0 SPECIAL FUNCTION
REGISTERS
........................................... 5-4
4.0 PORT STRUCTURES AND
OPERATION
........................................... 5-7
4.1 [/0 Configurations............................ 5-7
4.2 Writing to a Port ............................... 5-8
4.3 Port Loadingand Interfacing.......... 5-1Cl
4.4 Read-Modify-Write Feature............ 5-10
4.5 Accessing External Memory .......... 5-10
5.0 TIMERWCOUNTERS
......................... 5-12
5.1 TIMER OAND TIMER 1.................5-12
5.2 TIMER 2......................................... 5-15
6.fl~l:~RAMMABLE COUNTER
..................................................5-18
6.1 PCA 16-Bit Timer/Counter ............. 5-20
6.2 Capture/Compare Modules............ 5-22
6.3 16-Bit Capture Mode...................... 5-24
6.4 16-Bit Software Timer Mode .......... 5-24
6.5 High Speed Output Mode .............. 5-25
6.6 Watchdog Tmer Mode................... 5-25
6.7 Pulse Width Modulator Mode......... 5-26
7.0 SERIAL INTERFACE ......................... 5-27
7.1 Framing Error Deteotion ................ 5-28
7.2 Multiprocessor Communications.... 5-28
7.3 Automatic Address Recognition..... 5-28
CONTENTS PAGE
7.4 Baud Rates.................................... 5-3o
7.5 Using llmer 1 to Generate Baud
Rates................................................ 5-30
7.6 Using Timer 2 to Generate Baud
Rates................................................ 5-30
8.0 INTERRUPTS.....................................5-32
8.1 External Interrupts ......................... 5-33
8.2 Timer Interrupts.............................. 5-33
8.3 PCA Interrupt................................. 5-33
8.4 Serial Porl Interrupt........................ 5-33
8.5 Interrupt Enable ............................. 5-33
8.6 Priority Level Structure ..................5-33
8.7 ResponseTime.............................. 5-37
9.0 RESET................................................5-37
9.1 Power-On Reset ............................ 5-38
10.0 POWER-SAVING MODES OF
OPERATION......................................... 5-38
10.1 idle Mode..................................... 5-38
10.2
Power Down Mode ...................... 5-40
10.3 Power Off Flag............................. 5-40
11.0 EPROM VERSIONS......................... 5-40
12.0 PROGRAM MEMORY LOCK........... 5-40
13.0 ONCE MODE
................................... 5-41
14.0 ON-CHIP OSCILLATOR................... 5-42
15.0 CPU
TIMING .................................... 5-43
5-1