Intel MCS 51 User Manual

i~.
87C51GBHARDWARE DESCRIPTION
TRxand TFx are controlbits in the SFRTCON.The
MODE1
GATExbitsarein TMOD. There are two different
GATE bits: one for Timer 1 (TMOD.7)and one for Mode 1 is the same as Mode 0, exeeptthat the Timer
TimerO(TMOD.3).
registerusesall Id-bits.In this mode,THxand TLxare
cascaded;thereis no presesler. Refer to Figure9.
The 13-bitregisterconsistsof all 8bitsof THx and the
lower5bits of TLx.The upper 3 bits of TLx are inde
As the countrolls overfrom all 1sto all 0s, it sets the
terminateand should be imored. %ttin~ the run tlaiz
timer interrupt fhz TFOor TF1. The countedinput is
(TRx)doesnot clear these-registers. - -
enabledto th~tim~rwhenTROor TRl = 1,and~ther
GATEx = Oor INTxpin = 1. (SettingGATE%= 1
Table5.TCON:Timer/CounterControlRegister
TCON
Address= 88H
Reset= 0000OOOOB
BitAddressable
TF1 TR1 TFO TRO IEI IT1 IEO ITO
Bfi 7 6 5 4 3 2 1 0
Symbol Function
TF1 Timer1overflowFlag.SetbyhardwareonTimer/Countaroverflow.Clearedbyhardware
whenprocessorvectoratointerruptroutine.
TR1 Timer1 Runcontrolbit.Set/clesredbysoftwaretoturnTimer/Counter1on/off.
TFO TimerOoverflowFlag.SetbyhardwareonTimer/CounterOoverflow.Clearedbyhardware
whenprocessorvectorstointerruptroutine.
TRO TimerORuncontrolbit.Set/clearedbysoftwaretoturnlimer/CounterOon/off.
IE1
Interrupt1flag.Setbyhardwarewhenexternalinterrupt1edgeisdetected(transmittedor
level-activated).Clearedwheninterruptprocessedonlyiftransition-activated.
IT1
Interrupt1Typecontrolbit.Set/clearedbysoftwaratospecifiyfallingedge/lowleveltriggered
externalinterrupt1.
IEO InterruptOflag.SetbyhardwarewhenexternalinterruptOedgeisdetected(transmittedor
level-activated).Clearedwheninterruptprocessedonlyiftransition-activated.
ITO InterruptOTypecontrolbit.Set/clearedbyaoftwaretospecifyfallingedge/lowleveltriggered
externalinterruptO.
Osc
I
270S97-11
Figure9.Timer/CounterOor 1InMode1:16-BitCounter
6-15

Intel MCS 51 Specifications

General

Architecture	8-bit
Number of Instructions	111
Clock Speed	12 MHz
Register Size	8-bit
Internal RAM	128 bytes
Internal ROM	4 KB
External Memory	64 KB
I/O Pins	32
Timers	2
Serial Port	1
Interrupts	5
Operating Voltage	5V
UART	Yes
Program Memory	4 KB
RAM	128 bytes
Instruction Set	CISC

Summary

MCS® 51 Family of Microcontrollers Architectural Overview

THE MCS®-51 INSTRUCTION SET

Provides an overview of the MCS®-51 instruction set, optimized for 8-bit control applications.

Interrupt Structure

Overview of the 8051 interrupt structure, sources, and vectoring.

MCS® 51 Programmer’s Guide and Instruction Set

MCS®-51 INSTRUCTION SET

Provides a summary of the 8051 instruction set, including mnemonics and operands.

8051, 8052 and 80C51 Hardware Description

TIMER/COUNTERS

Describes Timer 0 and Timer 1, including operating modes and control registers.

8XC52/54/58 Hardware Description

8XC51FX Hardware Description

PORT STRUCTURES AND OPERATION

Details port structures, I/O configurations, and external memory access.

SERIAL INTERFACE

Covers serial port modes, framing error detection, and baud rate generation.

87C51GB Hardware Description

SPECIAL FUNCTION REGISTERS

Provides a map of the SFR space and their reset values.

I/O PORTS

TIMERS/COUNTERS

PROGRAMMABLE COUNTER ARRAY

SERIAL PORT

Details the serial port's modes, framing error detection, and baud rates.

INTERRUPTS

Covers interrupt sources, enable registers, and priority levels.

RESET

83C152 HARDWARE DESCRIPTION

GLOBAL SERIAL CHANNEL

DMA OPERATION

INTERRUPT STRUCTURE