Intel MCS 51 User Manual

87C51GB HARDWARE DESCRIPTION
Theclockinputcan be selectedfromthe followingfour
modes:
Oscillatorfraquancy/ 12:
ThePCA timer increments once per machine cycle.
With a 16 MIiz crystal, the timer increments evety
750m.
Oscillatorfrequency/ 4:
The PCA timer increments three times per machine
cycle. With a 16 MHz crystal, the timer increments
every250ns.
TimerOoverflows:
ThePCA timer increments wheneverTimer O over-
flows. This mode allows a programmableinput fre-
quencyto the PCA.
Externalinput:
ThePCA timer incrementswhena l-to-Otransition is
detected on the ECI pin (P1.2).The maximuminput
frequencyin this modeis oscillatorfrequency/ 8.
The mode register CMOD (Table 12) contains the
CountPulseSelectbits(CPS1and CPSO)to specifythe
clock input. This register also contains the ECF bit
whichenables the PCA counter overflowto generate
the PCA interrupt. In addition,the userhas the option
ofturning off the PCA timer duringIdle Modeby set-
tingthe CounterIdle bit (CIDL). This can further re-
ducepowerconsumptionby an additional30%.
The CCON(Table 13)registercontainstwo more bits
whichare
associatedwiththe PCAtimer/munter. The
CF bit gets set by hardware when the counter over-
flows,and the CRbit isset or clearedto turn the coun-
teron or off.
Table12.CMOD:PCACounterModeRegister
CMOD Address= OD9H
ResetValue= OOXXXOOOB
NotBitAddressable
CIDL
WDTE —l—
—
CPS1
CPSO
ECF
1
Bit 7 6 5
4
3
2
1
0
symbol Funotion
CIDL Canter Idlecontrol:CIDL= OprogramsthePCACountertocontinuefunctioningduring
idleMode.CIDL= 1programsittobegatedoffduringidle.
WDTE WatchdogTimerEnable:WDTE= OdiaablesWatchdogTimerfunctiononPCAModule4.
WDTE= 1enablesit.
—
Notimplemented,reservedforfutureuse.*
CPS1
PCACountPulseSelectbit1.
CPSO
PCACountPulseSaIectbitO.
CPS1 CPSO SelectedPCAInput**
o 0
Internal clock, Foac+ 12
0
1
Internalclock,FOSC+4
1 0
Timer Ooverflow
1 1 External ciookat EC1/Pl.2 pin (max. rate = Fosc+8)
ECF
PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generste an
interrupt. ECF = Odisables that funotion of CF.
NOTE:
“Usarsoftwareshould
notwriteIs to reservedbits.These bits maybe used in future 8051familyproductstoinvoke
newfeatures.
In that case, the resetor inactivevalue of the newbitwillbe O,and itsactivevaluewill be 1. The value
read froma reservedbitis indeterminate.
..F~ = ~llator frSIJUenCY
6-25

Intel MCS 51 Specifications

General

Architecture	8-bit
Number of Instructions	111
Clock Speed	12 MHz
Register Size	8-bit
Internal RAM	128 bytes
Internal ROM	4 KB
External Memory	64 KB
I/O Pins	32
Timers	2
Serial Port	1
Interrupts	5
Operating Voltage	5V
UART	Yes
Program Memory	4 KB
RAM	128 bytes
Instruction Set	CISC

Summary

MCS® 51 Family of Microcontrollers Architectural Overview

THE MCS®-51 INSTRUCTION SET

Provides an overview of the MCS®-51 instruction set, optimized for 8-bit control applications.

Interrupt Structure

Overview of the 8051 interrupt structure, sources, and vectoring.

MCS® 51 Programmer’s Guide and Instruction Set

MCS®-51 INSTRUCTION SET

Provides a summary of the 8051 instruction set, including mnemonics and operands.

8051, 8052 and 80C51 Hardware Description

TIMER/COUNTERS

Describes Timer 0 and Timer 1, including operating modes and control registers.

8XC52/54/58 Hardware Description

8XC51FX Hardware Description

PORT STRUCTURES AND OPERATION

Details port structures, I/O configurations, and external memory access.

SERIAL INTERFACE

Covers serial port modes, framing error detection, and baud rate generation.

87C51GB Hardware Description

SPECIAL FUNCTION REGISTERS

Provides a map of the SFR space and their reset values.

I/O PORTS

TIMERS/COUNTERS

PROGRAMMABLE COUNTER ARRAY

SERIAL PORT

Details the serial port's modes, framing error detection, and baud rates.

INTERRUPTS

Covers interrupt sources, enable registers, and priority levels.

RESET

83C152 HARDWARE DESCRIPTION

GLOBAL SERIAL CHANNEL

DMA OPERATION

INTERRUPT STRUCTURE