Intel MCS 51 User Manual

i~.
87C51GB HARDWAREDESCRIPTION
Noneof the SEP SFRSare bit addressable.However,
the individualbits of SEPSTATand SEPCONare sig-
nificantandhavesymbolicnamesassociatedwiththem
as shown.The meanin
g of thesebits are:
SEPE — SEP Enablebit
SEPREN— SEP ReceiveENable
CLKPOL—
CLOCKPOLarity
CLKPH — CLOCKPHaae
SEPS1 — SEPSpeedselect 1
SEPSO — SEPSpeedselectO
SEPFWR—SEP Fault duringWRite
SEPFRD— SEP Fault duringReaD
SEPIF — SEP Interrupt Flag
9.1 ProgrammableModesand
ClockOptions
The four programmablemodesdeterrmn“ e the inactive
levelof the clock
pinand whichedgeof the clockis
used for transmissionor reception.Thesefour modes
are shownin Figure 31.Table 19showshowthe modes
are determined.
Table19.Determination’ofSEPModes
CLKPOL
CLKPH
SEPMode
1
0
0
SEPMODEO
o
1 SEPMODE1“
1
0 SEPMODE2
1
1 SEPMODE3*
Thefourclockoptionsdeterminethe rate at whichdata
is shifted out of or into the SEP. All four rates are
fractionsofthe oscillatorfrequency.Table20showsthe
variousrates that can be sel&tecfor the SEP.
Tabfe20. SEPDataRates
m
SEPMODEO
....~....
CLOCK
SEPMOOE2
—---~---—
CLOCK
“TAsAMPLED~
DATAOUTPUT —
“ SEPMOOE1
—...~....
CLOCK
“ SEPMODE3
—“--~---—
CLOCK
Figure31.SEPModes
6-39

Intel MCS 51 Specifications

General

Brand	Intel
Model	MCS 51
Category	Microcontrollers
Language	English