intd.
87C51GB HARDWARE DESCRIPTION
9.2 SEPTransmissionor Reception
To trananu“tor receivea byte the user shouldinitialize
the SEPmode(CLKPOLandCLKPH),clockfrequen-
cy (SEPS1andSEPSO),and enablethe SEP(SEPE).A
transmissionthen occurs if the user loads data into
SEPDATA. A reception occurs
if the user seta
SEPREN whileSEPDATAis empty and a trammrs
“.
aionis not inprogress.When8 bits havebeenreceived
SEPRENwillbe clearedby hardware. Oncethe trans-
mission or receptionis mmple@ SEPIF wiUbe set.
SEPIF remainsset until cleared by software.SEPIF is
also the sourceofthe SEPinterrupt. Data is transmit-
ted and rSCeiVedMSBfirst.
If the user attempts to read or write the SEPDATA
registeror writeto the SEPCONregisterwhilethe SEP
is transmitting or receivingan error bit is set. The
SEPFWRbit issetifthe actionoccurredwhilethe SEP
was transmitting.The SEPFRDbit is set if the action
occurredwhilethe SEPwas receiving.There is no in-
terrupt associatedwiththeseerror bits.Thebit remains
set until clearedby aotlware. The attempted read or
write ofthe registeris ignored.The receptionof trans-
missionthat wasin progresswillnot be affected.
10.0 HARDWAREWATCHDOGTIMER
The hardware WatchDog Timer (WDT) rmets the
gXC51GBwhenit overflows.The WDTis intendedas
a recoverymethodinsituationswherethe CPUmaybe
subjectedto a softwareupset.The WDT consistsof a
14-bit counter and the WatchDog Timer ReSeT
(WDTRST)SFR.The WDT is alwaysenabledand in-
crements whilethe oscillator is running. There is no
wayto disabletheWDT.Thismeansthat theusermust
still service the WDT while testing or debuggingan
appli~tion. The WDT is loaded tith
o Whm the
8XC51GBexitsreset. The WDT describd in this sec-
tion is not the WatchdogTimer associatedwith PCA
module4. The WDTdoesnot drive the Reset pin.
10.1 UsingtheWDT
Since the WDT is automatically enabled while the
processoris running,the user only needs to be con-
cerned with servicingit. The 14-bitcounteroverflows
whenit rcachcs16383(3FFFH).The WDTincrements
once everymachinecycle. This means the user must
reaet the WDT at least every 16383machinecycles.If
the user doesnot wish to use the functionalityof the
WDT in an application,a timer interrupt can be used
to reset the WDT. To reset the WDT the user must
write OIEH and OEIH to WDTRST. WDTRSTis a
write onlyregister.The WDT count cannotbe read or
written.Usinga timerinterrupt is not recommendedin
aPPfimtiomthat makeuse of the WDT becauseinter-
rupt maystillbeserviced,evenaftera softwareupset.
TomakethebmtuseoftheWDT,it shouldbeserviced
in those sectionsof codethat will periodicallybe exe
cutexiwithinthe timerequiredto preventa WDTreset.
10.2 ~fT DuringPowerDownand
In
PowerDownmodethe oscillatorstops,whichmeans
the WDT also stops.While in Power Down the user
dcesnot needto servicethe WDT.Thereare twometh-
ods of exitingPowerDown: by a reset or via a level
activated externrdinterrupt which is enabledprior to
entering PowerDown.If Power Down is exited with
rest, servicingoftheWDTshouldoccuras it normally
does wheneverthe 8XC51GBis reset. ExitingPower
Down with art interrupt is significantlydifferent.The
interruptis held low which brings the deviceout of
Power Down and starts the oscillator.The user must
holdthe interruptlowlongenoughfor the oscillatorto
stabilise.Whenthe interrupt is broughthigh,the inter-
rupt ia serviced.To prevent the WDT from resetting
the devicewhiletheinterrupt pinis heldlow,the WDT
is not started until the interrupt is pulled high. It is
suggested
thatthe WDT be react during the interrupt
seMce routine for the interrupt used to exit Power
Down.
To ensure that the WDT doeanot overflowwithin a
fewstatesofexitingofpowerdown,it isbeatto resetthe
WDTjust beforeenteringpowerdown.
In Idle mode,the oscillatorcontinuesto rum To pre-
vent the WDT from resetting the 8XC51GBwhile in
Idle, the user shouldalways set up a timer that will
periodicallyexit MI%service the WDT, and re-enter
Idle mcde.
11.0 OSCILLATORFAIL DETECT
The OscillatorFail Detect (OFD) circuitry keeps the
8XC51GBin reset whenthe oscillatorspeedis below
the OFD triggerfrequency.TheOFD triggerfrequency
is shown in the data sheet as a minimumand maxi-
mum.If theoscillatorfrequencyis belowtheminimum,
the deviceis heldin reset. If the oscillatorfrequencyis
greater thsn the tnsximtunjthe devicewillnot be
held
in
reset. If the frequencyis betweenthe minimumand
maximum,it is indeterminatewhether the devicewill
be held in reset or not.
The OFD is automatically enabled when the device
corneaout ofresetor whenPowerDownis exitedwith
a reset or an interrupt.
The OFD is intended to function only in situations
where
thereis a grossfailureof the oscillator,suchas a
6-40
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