Intel Stratix 10 - Page 152

a. Write 0x84[7:0] = 0x33.
b. Write 0x85[7:0] = 0x03.
c. Write 0x86[7:0] = 0x19.
d. Write 0x87[7:0] = 0x00.
e. Write 0x90[0] = 1’b1.
f. Read 0x8A[7]. It should be 1.
g. Read 0x8B[0] until it changes to 0.
h. Write 0x8A[7] to 1 to clear the 0x8A[7] flag.
10. Load pattern [79:70].
a. Write 0x84[7:0] = 0xCC.
b. Write 0x85[7:0] = 0x00.
c. Write 0x86[7:0] = 0x19.
d. Write 0x87[7:0] = 0x00.
e. Write 0x90[0] = 1’b1.
f. Read 0x8A[7]. It should be 1.
g. Read 0x8B[0] until it changes to 0.
h. Write 0x8A[7] to 1 to clear the 0x8A[7] flag.
11. Load the TX PRBS generator with your pattern.
a. Write 0x84[7:0] = 0x27.
b. Write 0x85[7:0] = 0x01.
c. Write 0x86[7:0] = 0x02.
d. Write 0x87[7:0] = 0x00.
e. Write 0x90[0] = 1’b1.
f. Read 0x8A[7]. It should be 1.
g. Read 0x8B[0] until it changes to 0.
h. Write 0x8A[7] to 1 to clear the 0x8A[7] flag.
12. Enable the PMA TX output.
a. Write 0x84[7:0] = 0x07.
b. Write 0x85[7:0] = 0x00.
c. Write 0x86[7:0] = 0x01.
d. Write 0x87[7:0] = 0x00.
e. Write 0x90[0] = 1’b1.
f. Read 0x8A[7]. It should be 1.
g. Read 0x8B[0] until it changes to 0.
h. Write 0x8A[7] to 1 to clear the 0x8A[7] flag.
8. Dynamic Reconfiguration Examples
UG-20056 | 2019.02.04
Intel
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Stratix
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10 E-Tile Transceiver PHY User Guide
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