Intel Stratix 10 - Page 162

Figure 97. Adaptation Working Flow
Transceiver
Power-up
Load PMA
Configuration
Check PMA
Configuration
Status
Start Initial or
Continuous
Adaptation
for chnl[i]
Check for Initial or
Continuous
Adaptation Status
for chnl[i]
To Load a Different
PMA Configuration
Timeout
PMA Analog
Reset
N=number of chnls?
Transceiver
in Required
Configuration
Y
N
In the above flow, the transceiver reset is required only for non-Hard PRBS designs,
meaning that the data is coming to the transceiver tile from the FPGA core.
Refer to Loading a PMA Configuration for more details.
Related Information
• PMA Adaptation on page 37
• PMA Bring Up Flow on page 69
• PMA Analog Reset on page 104
8. Dynamic Reconfiguration Examples
UG-20056 | 2019.02.04
Intel
®
Stratix
®
10 E-Tile Transceiver PHY User Guide
Send Feedback
162