Intel Stratix 10 User Manual

9.3.2. Set PRBS Mode and Internal or Serial Loopback......................................... 186
9.3.3. Start Adaptation and Put PMA in Mission Mode........................................... 186
9.3.4. Read the Physical Channel Number...........................................................187
9.4. Supported Data Rate Ratios for PMA Attribute Codes 0x0005 and 0x0006.................. 187
9.5. RS-FEC Registers............................................................................................... 190
9.5.1. rsfec_top_clk_cfg................................................................................... 193
9.5.2. rsfec_top_tx_cfg.................................................................................... 194
9.5.3. rsfec_top_rx_cfg.................................................................................... 195
9.5.4. tx_aib_dsk_conf.....................................................................................196
9.5.5. rsfec_core_cfg....................................................................................... 196
9.5.6. rsfec_lane_cfg....................................................................................... 197
9.5.7. tx_aib_dsk_status.................................................................................. 197
9.5.8. rsfec_debug_cfg.................................................................................... 198
9.5.9. rsfec_lane_tx_stat..................................................................................199
9.5.10. rsfec_lane_tx_hold............................................................................... 199
9.5.11. rsfec_lane_tx_inten.............................................................................. 200
9.5.12. rsfec_lane_rx_stat................................................................................200
9.5.13. rsfec_lane_rx_hold............................................................................... 201
9.5.14. rsfec_lane_rx_inten.............................................................................. 202
9.5.15. rsfec_lanes_rx_stat.............................................................................. 203
9.5.16. rsfec_lanes_rx_hold..............................................................................203
9.5.17. rsfec_lanes_rx_inten.............................................................................204
9.5.18. rsfec_ln_mapping_rx............................................................................ 204
9.5.19. rsfec_ln_skew_rx................................................................................. 205
9.5.20. rsfec_cw_pos_rx.................................................................................. 205
9.5.21. rsfec_core_ecc_hold............................................................................. 205
9.5.22. rsfec_err_inj_tx................................................................................... 206
9.5.23. rsfec_err_val_tx...................................................................................206
9.5.24. rsfec_corr_cw_cnt (Low)....................................................................... 207
9.5.25. rsfec_corr_cw_cnt (High)...................................................................... 207
9.5.26. rsfec_uncorr_cw_cnt (Low)....................................................................208
9.5.27. rsfec_uncorr_cw_cnt (High)................................................................... 208
9.5.28. rsfec_corr_syms_cnt (Low)....................................................................208
9.5.29. rsfec_corr_syms_cnt (High)................................................................... 209
9.5.30. rsfec_corr_0s_cnt (Low)........................................................................209
9.5.31. rsfec_corr_0s_cnt (High)....................................................................... 210
9.5.32. rsfec_corr_1s_cnt (Low)........................................................................210
9.5.33. rsfec_corr_1s_cnt (High)....................................................................... 210
9.6. Register Map Revision History.............................................................................. 211
A. E-Tile Channel Placement Tool.................................................................................... 212
A.1. E-Tile Channel Placement Tool Revision History...................................................... 212
B. PMA Direct PAM4 30 Gbps to 57.8 Gbps Implementation............................................ 214
B.1. Building Blocks and Considerations.......................................................................214
B.2. Starting a New Intel Quartus Prime Pro Edition Design............................................ 218
B.3. Selecting the Configuration Clock Source...............................................................219
B.4. Instantiating the Transceiver Native PHY IP............................................................220
B.5. Instantiating the In-system Sources and Probes Intel FPGA IP................................. 223
B.6. Making the Top Level Connection..........................................................................224
B.7. Assigning Pins................................................................................................... 226
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Intel
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Stratix
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10 E-Tile Transceiver PHY User Guide
5

Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English