Intel Stratix 10 User Manual

Parameter Min Max Initial Adaptation Continuous
Adaptation
Manual
Optimization
Possible
Firmware
Default
CTLE LF Max 0 15 N/A N/A N/A 15
GainHF 0 15 Yes Yes Yes 0
Limit CTLE HF min 0 15 N/A N/A N/A 0
Limit CTLE HF man 0 15 N/A N/A N/A 15
GS1 0 3 No No Yes 0
GS2 0 3 No No Yes 0
RF_P2 -10
(8)
10 Yes No No 0
RF_P2_MIN -10
(8)
10 N/A N/A N/A -10
RF_P2_MAX -10
(8)
10 N/A N/A N/A 10
RF_P1 0 15 Yes Yes No 0
RF_P1_MIN 0 15 N/A N/A N/A 0
RF_P1_MAX 0 15 N/A N/A N/A 15
RF_P0 -15
(8)
15 Yes Yes No 0
RF_B1 0 8 Yes Yes Yes 0
RF_B0 0 5 No Yes Yes 0
RF_B0T — — — — — —
RF_A
NRZ and PAM4
Increment/decrement
by 10 (applies to both
min and max values)
100 160 — — Yes 160
Related Information
• PMA Bring Up Flow on page 69
• PMA Register Map on page 165
• 0x000A: Receiver Tuning Controls on page 175
• PMA Receiver Equalization Adaptation Usage Model on page 147
• PMA Receiver Equalization Adaptation Usage Model on page 147
• 0x000A: Receiver Tuning Controls on page 175
3.1.2.2. Clock Data Recovery (CDR) Block
Clocking resources in the receiver enable the clock data recovery feature in Intel
Stratix 10 devices. The CDR block locks to the received signal and extracts the
transmitted data sequence by recovering the clocking information from the distorted
received signal.
(8)
Two’s complement, 16-bits
3. Intel Stratix 10 E-Tile Transceiver PHY Architecture
UG-20056 | 2019.02.04
Intel
®
Stratix
®
10 E-Tile Transceiver PHY User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English