Intel Stratix 10 - Page 81

Figure 45. E-Tile Floor Plan Configurations
This figure illustrates the placement of various architecture blocks, and the modes supported in the RS-FEC
blocks.
Note:
1. This block cannot be used in combination with EHIP_CORE - fractured bypass.
(1)
3. Intel Stratix 10 E-Tile Transceiver PHY Architecture
UG-20056 | 2019.02.04
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10 E-Tile Transceiver PHY User Guide
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