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Intel Stratix 10 User Manual
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Figure 45.
E-Tile Floor Plan Configurations
This figure illustrates the placement of v
arious architecture blocks, and the modes supported in the RS-FEC
blocks.
Note:
1. This block cannot be used in combination with EHIP_CORE - fr
actured bypass.
(1)
3. Intel Stratix 10 E-Tile Transceiver PHY Architecture
UG-20056 | 2019.02.04
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Intel
®
Stratix
®
10 E-
Tile T
ransceiver PHY User Guide
81
80
82
Table of Contents
Default Chapter
2
Table of Contents
2
1 Intel ® Stratix ® 10 E-Tile Transceiver PHY Overview
7
Supported Features
7
E-Tile Layout in Stratix 10 Device Variants
8
Intel Stratix 10 TX H-Tile and E-Tile Configurations
8
Stratix 10 MX H-Tile and E-Tile Configurations
10
Transceiver Counts in Stratix 10 TX/MX Devices
10
E-Tile Building Blocks
11
GXE Transceiver Channel
12
GXE Channel Usage
13
Reference Clocks
15
Ethernet Hard IP (EHIP)
19
Supported Applications/Modes
21
Feature Comparison between Transceiver Tiles
21
Intel Stratix 10 E-Tile Transceiver PHY Overview Revision History
22
2 Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices
24
Transceiver Design Flow in the Native PHY IP Core
24
E-Tile Native PHY IP Core
25
Configuring the Native PHY IP Core
25
General and Datapath Parameters
27
PMA Parameters
29
Core Interface Options
33
PMA Interface
36
PMA Adaptation
37
Reed Solomon Forward Error Correction (RS-FEC) Parameters
41
Reset Parameters
45
Dynamic Reconfiguration Parameters
46
Port Information
49
PLL Mode
52
Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices Revision History
54
3 Intel Stratix 10 E-Tile Transceiver PHY Architecture
56
Physical Medium Attachment (PMA) Architecture
57
Transmitter PMA
59
Receiver PMA
64
PMA Tuning
68
Loopback Modes
74
PMA Interface
76
TX PMA Bonding
77
Unused Transceiver Channel
79
Physical Coding Sublayer (PCS) Architecture
79
Reed Solomon Forward Error Correction (RS-FEC) Architecture
79
RS-FEC Modes
80
Intel Stratix 10 E-Tile Transceiver PHY Architecture Revision History
85
4 Clock Network
86
Reference Clock Pins
86
QSF Assignments for Reference Clock Pins
89
Core Clock Network Use Case
89
Single 25 Gbps PMA Direct Channel (with FEC) Within a Single FEC Block
90
Single 10 Gbps PMA Direct Channel (Without FEC)
90
Four 25 Gbps PMA Direct Channel (with FEC) Within a Single FEC Block
91
PMA Direct 25 Gbps X 4 (FEC Off)
94
PMA Direct 10.3125 Gbps X 4
95
PMA Direct 100GE Gbps (25 Gbps X 4 Per Lane) (FEC On)
95
Clock Network Revision History
97
5 PMA Calibration
98
PMA Calibration Revision History
99
6 Resetting Transceiver Channels
100
When Is Reset Required
100
How Do I Reset
100
Resetting the Intel Stratix 10 E-Tile Transceiver
101
Selecting the Reset Controller's Clock Source
102
Reset Block Architecture
102
PMA Analog Reset
104
High Level Specification
105
Automatic Reset Mode
105
Manual Reset Mode
107
Reset Controller Bypass
112
Intel Quartus Prime Instantiated Transceiver Reset Sequencer
114
Block Diagrams
115
Interfaces
117
Reset Parameters in the Native PHY GUI
117
HDL Ports/Interfaces
117
Resetting Transceiver Channels Revision History
118
7 Dynamic Reconfiguration
119
Dynamically Reconfiguring Channel Blocks
120
Interacting with the Dynamic Reconfiguration Interface
120
Unsupported Features
121
Reading from the Dynamic Reconfiguration Interface
121
Writing to the Dynamic Reconfiguration Interface
122
Multiple Reconfiguration Profiles
123
Reconfiguration Files
124
Embedded Reconfiguration Streamer
125
Arbitration
126
Recommendations for PMA Dynamic Reconfiguration
127
Steps to Perform Dynamic Reconfiguration
127
PMA Attribute Details
129
Dynamic Reconfiguration Flow for Special Cases
129
Switching Reference Clocks
129
Ports and Parameters
131
Embedded Debug Features
135
Altera Debug Master Endpoint (ADME)
135
Optional Dynamic Reconfiguration Logic
136
Timing Closure Recommendations
136
Transceiver Register Map
137
Loading IP Configuration Settings
137
Loading IP Configuration Settings Process
137
Alternative Method for Setting PMA Attributes
138
Dynamic Reconfiguration Revision History
138
8 Dynamic Reconfiguration Examples
140
Reconfiguring the Duplex PMA Using the Reset Controller in Automatic Mode
140
PRBS Usage Model
143
PMA Error Injection
146
PMA Receiver Equalization Adaptation Usage Model
147
User-Defined Pattern Example
150
Configuring the Attenuation Value (VOD)
153
Configuring the Post Emphasis Value
153
Configuring Pretap1 Values
154
Inverting TX Polarity for the PMA Driver
154
Inverting RX Polarity for the PMA Driver
154
Configuring a PMA Parameter Tunable by the Adaptive Engine
155
Configuring a PMA Parameter Using Native PHY IP
157
PMA Bring up Flow Using Native PHY IP
157
Native PHY IP GUI Details
158
Loading a PMA Configuration
163
Dynamic Reconfiguration Examples Revision History
163
9 Register Map
165
PMA Register Map
165
PMA Capability Registers
165
PMA Control and Status Registers
166
PMA AVMM Registers
167
PMA Attribute Codes
170
0X0001: PMA Enable/Disable
170
0X0002: PMA PRBS Settings
171
0X0003: Data Comparison Set up and Start/Stop
172
0X0005: TX Channel Divide by Ratio
173
0X0006: RX Channel Divide by Ratio
173
0X0008: Internal or Serial Loopback and Reverse Parallel Loopback Control
174
0X000A: Receiver Tuning Controls
175
0X0011: PMA TX/RX Calibration
175
0X0013: TX/RX Polarity and Gray Code Encoding
176
0X0014: TX/RX Width Mode
177
0X0015: TX Equalization
177
0X0017: Error Counter Reset
178
0X0018: Status/Debug Register
179
0X0019: Status/Debug Register Next Write Field
179
0X001A: Status/Debug Register Next Read Field
180
0X001B: TX Error Injection Signal
180
0X001C: Incoming RX Data Capture
180
0X001E: Error Count Status
181
0X002B: RX Termination and TX Driver Tri-State Behavior
181
0X0126: Read Receiver Tuning Parameters
182
Reading and Writing PMA Analog Parameters Using Attributes
182
PMA Registers 0X200 to 0X203 Usage
184
PMA Analog Reset
186
Set PRBS Mode and Internal or Serial Loopback
186
Start Adaptation and Put PMA in Mission Mode
186
Read the Physical Channel Number
187
Supported Data Rate Ratios for PMA Attribute Codes 0X0005 and 0X0006
187
RS-FEC Registers
190
Rsfec_Top_Clk_Cfg
193
Rsfec_Top_Tx_Cfg
194
Rsfec_Top_Rx_Cfg
195
Tx_Aib_Dsk_Conf
196
Rsfec_Core_Cfg
196
Rsfec_Lane_Cfg
197
Tx_Aib_Dsk_Status
197
Rsfec_Debug_Cfg
198
Rsfec_Lane_Tx_Stat
199
Rsfec_Lane_Tx_Hold
199
Rsfec_Lane_Tx_Inten
200
Rsfec_Lane_Rx_Stat
200
Rsfec_Lane_Rx_Hold
201
Rsfec_Lane_Rx_Inten
202
Rsfec_Lanes_Rx_Stat
203
Rsfec_Lanes_Rx_Hold
203
Rsfec_Lanes_Rx_Inten
204
Rsfec_Ln_Mapping_Rx
204
Rsfec_Ln_Skew_Rx
205
Rsfec_Cw_Pos_Rx
205
Rsfec_Core_Ecc_Hold
205
Rsfec_Err_Inj_Tx
206
Rsfec_Err_Val_Tx
206
Rsfec_Corr_Cw_Cnt (Low)
207
Rsfec_Corr_Cw_Cnt (High)
207
Rsfec_Uncorr_Cw_Cnt (Low)
208
Rsfec_Uncorr_Cw_Cnt (High)
208
Rsfec_Corr_Syms_Cnt (Low)
208
Rsfec_Corr_Syms_Cnt (High)
209
Rsfec_Corr_0S_Cnt (Low)
209
Rsfec_Corr_0S_Cnt (High)
210
Rsfec_Corr_1S_Cnt (Low)
210
Rsfec_Corr_1S_Cnt (High)
210
Register Map Revision History
211
E-Tile Channel Placement Tool
212
E-Tile Channel Placement Tool Revision History
212
PMA Direct PAM4 30 Gbps to 57.8 Gbps Implementation
214
Building Blocks and Considerations
214
Starting a New Intel Quartus Prime Pro Edition Design
218
Selecting the Configuration Clock Source
219
Instantiating the Transceiver Native PHY IP
220
Instantiating the In-System Sources and Probes Intel FPGA IP
223
Making the Top Level Connection
224
Assigning Pins
226
Bringing up the Board
226
Debug Tools
227
Monitoring Transceiver Signals
227
B.9. Debug Tools
227
PMA Direct PAM4 30 Gbps to 57.8 Gbps Implementation Revision History
228
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Configuration User Guide
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Intel Stratix 10 Specifications
General
Brand
Intel
Model
Stratix 10
Category
Control Unit
Language
English
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