Intel Stratix 10 User Manual

Figure 46. Datapath Routing for RS-FEC Configurations
Supported RS-FEC configurations are shown inTable 37 on page 80.
P
T
P
P
T
P
EHIP_TOP
EHIP_TOP
PMA Direct
PMA Direct
RS-FEC
Notes:
1. Not all datapath combinations are available.
2. Datapath enablement depends on the configuration you are implementing. Refer to the E-Tile Channel
Placement tool for possible configurations.
3. This FEC block can only be used in aggregate mode with FEC direct application (e.g. 128GFC Fibre-Channel).
This FEC block cannot be used in in aggregate mode with EHIP_CORE because there is no EHIP_CORE in this location.
Legend:
= EHIP_CORE
= FEC
= EHIP_LANE
Interconnect
Interconnect Interconnect
Interconnect
Interconnect
Interconnect
InterconnectInterconnectInterconnect
FPGA Core
EMIB
EMIB
EMIB
EMIB
EMIB
EMIB
EMIB
EMIB
EMIB
EMIB
EMIB
EMIB
RS-FEC
RS-FEC
PMA CH0
PMA CH1
PMA CH2
PMA CH3
PMA CH4
PMA CH5
PMA CH6
PMA CH7
PMA CH8
PMA CH9
PMA CH10
PMA CH11
FEC
(528, 514)
or (544, 514)
(Aggregate:
100G)
(Fractured:
25G)
FEC
(528, 514) or
(544, 514)
(Aggregate:
100G)
(Fractured:
25G)
EHIP_CORE
(100G MAC
+ PCS)
EHIP_LANE
x4
(10G /25G)
MAC + PCS
EHIP_LANE
x2
(10G /25G)
MAC + PCS
EHIP_LANE
x2
(10G /25G)
MAC + PCS
EHIP_LANE
x4
(10G /25G)
MAC + PCS
EHIP_CORE
(100G MAC
+ PCS)
6
7
8
9
10
11
8
9
10
11
6
7
6
7
6
7
4
5
6
7
2
3
4
5
0
1
2
3
0
1
8
9
10
11
8
9
10
11
8
9
10
11
8
9
10
11
8
9
10
11
6
7
4
5
4
5
4
5
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
4
5
FEC
(3)
(528, 514) or
(544, 514)
(Aggregate:
100G)
(Fractured:
25G)
Table 38. FEC Block Modes by Channel
This table corresponds to Figure 47 on page 83 and Figure 48 on page 84
Channels
FEC Block Mode FEC Receives Data From
0 to 3 Aggregate EHIP_CORE
4 to 5 Bypass N/A
continued...
3. Intel Stratix 10 E-Tile Transceiver PHY Architecture
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English