Intel Stratix 10 User Manual

power-up, which may or may not be the same as what is configured in the transceiver
IP. A difference in the configured refclk in the IP compared to the available refclk
on the board can cause unexpected transitions on the E-Tile TX output.
Make sure you are okay with this behavior until the refclk frequencies are set
correctly followed by the recommended reset and device configuration steps as per
PMA Analog Reset. If the unexpected transitions are not acceptable, you can disable
the transceiver TX output by writing the attribute code 0x0001 with data 0x0003 after
power-up. The E-Tile TX may still give some unexpected transitions between the
power-up phase until the attribute code 0x0001 is written.
After correctly configuring back the on-board reference clock, follow the recommended
reset and device configuration steps as per PMA Analog Reset to reset the internal
controller. Refer to the Register Map for more details on attribute codes and data.
4. Clock Network
UG-20056 | 2019.02.04
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10 E-Tile Transceiver PHY User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English