Intel Stratix 10 User Manual

Figure 50. REFCLK LVPECL Pins
This diagram illustrates the nine refclk pins and the reference clock network within a given Intel Stratix 10 E-
Tile.
Transmitter
Receiver
Transmitter
Receiver
Transceiver
Transceiver
Reference Clock
Channels
23 to 0
Reference clock network within an E-Tile
Nine REFCLK LVPECL Pins
REFCLK_0
refclk_in_A
refclk_in_B
refclk_in_A
refclk_in_B
REFCLK_8
+
–
Divide
by 2
LVPECL
+
–
Divide
by 2
LVPECL
+
–
Divide
by 2
LVPECL
+
–
Divide
by 2
LVPECL
+
–
Divide
by 2
LVPECL
+
–
Divide
by 2
LVPECL
+
–
Divide
by 2
LVPECL
+
–
Divide
by 2
LVPECL
+
–
Divide
by 2
LVPECL
For details on LVPECL standard spec, refer to Intel Stratix 10 Device Datasheet.
Related Information
• PMA Analog Reset on page 104
• Register Map on page 165
• Intel Stratix 10 Device Datasheet
• Intel Stratix 10 Device Family Pin Connection Guidelines
• My Intel support
4. Clock Network
UG-20056 | 2019.02.04
Intel
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10 E-Tile Transceiver PHY User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English