UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 20 December 2013 825 of 841
continued >>
NXP Semiconductors
UM10360
Chapter 35: Supplementary information
12.4.2 Software interface. . . . . . . . . . . . . . . . . . . . . 272
12.4.2.1 Register map . . . . . . . . . . . . . . . . . . . . . . . . 272
12.4.2.2 USB Host Register Definitions. . . . . . . . . . . 273
Chapter 13: LPC176x/5x USB OTG
13.1 How to read this chapter. . . . . . . . . . . . . . . . 274
13.2 Basic configuration . . . . . . . . . . . . . . . . . . . . 274
13.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 274
13.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
13.5 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 275
13.6 Modes of operation . . . . . . . . . . . . . . . . . . . . 275
13.7 Pin configuration . . . . . . . . . . . . . . . . . . . . . . 276
13.7.1 Connecting the USB port to an external OTG
transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . 276
13.7.2 Connecting USB as a host . . . . . . . . . . . . . . 277
13.7.3 Connecting USB as device. . . . . . . . . . . . . . 277
13.8 Register description . . . . . . . . . . . . . . . . . . . 278
13.8.1 USB Interrupt Status Register (USBIntSt -
0x5000 C1C0) . . . . . . . . . . . . . . . . . . . . . . . 278
13.8.2 OTG Interrupt Status Register (OTGIntSt -
0x5000 C100). . . . . . . . . . . . . . . . . . . . . . . . 279
13.8.3 OTG Interrupt Enable Register (OTGIntEn -
0x5000 C104). . . . . . . . . . . . . . . . . . . . . . . . 279
13.8.4 OTG Interrupt Set Register (OTGIntSet -
0x5000 C20C) . . . . . . . . . . . . . . . . . . . . . . . 280
13.8.5 OTG Interrupt Clear Register (OTGIntClr -
0x5000 C10C) . . . . . . . . . . . . . . . . . . . . . . . 280
13.8.6 OTG Status and Control Register (OTGStCtrl -
0x5000 C110) . . . . . . . . . . . . . . . . . . . . . . . . 280
13.8.7 OTG Timer Register (OTGTmr - 0x5000
C114) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
13.8.8 OTG Clock Control Register (OTGClkCtrl -
0x5000 CFF4). . . . . . . . . . . . . . . . . . . . . . . . 281
13.8.9 OTG Clock Status Register (OTGClkSt -
0x5000 CFF8). . . . . . . . . . . . . . . . . . . . . . . . 282
13.8.10 I2C Receive Register (I2C_RX - 0x5000
C300) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
13.8.11 I2C Transmit Register (I2C_TX - 0x5000
C300) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
13.8.12 I2C Status Register (I2C_STS - 0x5000
C304) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
13.8.13 I2C Control Register (I2C_CTL - 0x5000
C308) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
13.8.14 I2C Clock High Register (I2C_CLKHI -
0x5000 C30C) . . . . . . . . . . . . . . . . . . . . . . . 286
13.8.15 I2C Clock Low Register (I2C_CLKLO -
0x5000 C310) . . . . . . . . . . . . . . . . . . . . . . . 286
13.8.16 Interrupt handling. . . . . . . . . . . . . . . . . . . . . 286
13.9 HNP support . . . . . . . . . . . . . . . . . . . . . . . . . 287
13.9.1 B-device: peripheral to host switching . . . . . 288
Remove D+ pull-up . . . . . . . . . . . . . . . . . . . . 290
Add D+ pull-up. . . . . . . . . . . . . . . . . . . . . . . . 291
13.9.2 A-device: host to peripheral HNP switching. 291
Set BDIS_ACON_EN in external OTG transceiver
293
Clear BDIS_ACON_EN in external OTG trans-
ceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Discharge V
BUS
. . . . . . . . . . . . . . . . . . . . . . . 294
Load and enable OTG timer . . . . . . . . . . . . . 295
Stop OTG timer . . . . . . . . . . . . . . . . . . . . . . . 295
Suspend host on port 1 . . . . . . . . . . . . . . . . . 295
13.10 Clocking and power management. . . . . . . . 295
13.10.1 Device clock request signals . . . . . . . . . . . . 296
13.10.1.1 Host clock request signals . . . . . . . . . . . . . . 297
13.10.2 Power-down mode support . . . . . . . . . . . . . 297
13.11 USB OTG controller initialization . . . . . . . . 297
Chapter 14: LPC176x/5x UART0/2/3
14.1 Basic configuration . . . . . . . . . . . . . . . . . . . . 299
14.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
14.3 Pin description. . . . . . . . . . . . . . . . . . . . . . . . 300
14.4 Register description . . . . . . . . . . . . . . . . . . . 300
14.4.1 UARTn Receiver Buffer Register (U0RBR -
0x4000 C000, U2RBR - 0x4009 8000, U3RBR -
0x4009 C000 when DLAB = 0). . . . . . . . . . . 302
14.4.2 UARTn Transmit Holding Register (U0THR -
0x4000 C000, U2THR - 0x4009 8000, U3THR -
0x4009 C000 when DLAB = 0). . . . . . . . . . . 302
14.4.3 UARTn Divisor Latch LSB register (U0DLL -
0x4000 C000, U2DLL - 0x4009 8000, U3DLL -
0x4009 C000 when DLAB = 1) and UARTn Divisor
Latch MSB register (U0DLM - 0x4000 C004,
U2DLL - 0x4009 8004, U3DLL - 0x4009 C004
when DLAB = 1). . . . . . . . . . . . . . . . . . . . . . 302
14.4.4 UARTn Interrupt Enable Register (U0IER -
0x4000 C004, U2IER - 0x4009 8004, U3IER -
0x4009 C004 when DLAB = 0) . . . . . . . . . . 303
14.4.5 UARTn Interrupt Identification Register (U0IIR -
0x4000 C008, U2IIR - 0x4009 8008, U3IIR -
0x4009 C008) . . . . . . . . . . . . . . . . . . . . . . . 304
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