NXP Semiconductors LPC1769 - Page 827

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User manual Rev. 3 — 20 December 2013 827 of 841
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NXP Semiconductors
UM10360
Chapter 35: Supplementary information
15.5 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 342
Chapter 16: LPC176x/5x CAN1/2
16.1 Basic configuration . . . . . . . . . . . . . . . . . . . . 344
16.2 CAN controllers . . . . . . . . . . . . . . . . . . . . . . . 344
16.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
16.3.1 General CAN features . . . . . . . . . . . . . . . . . 344
16.3.2 CAN controller features . . . . . . . . . . . . . . . . 345
16.3.3 Acceptance filter features. . . . . . . . . . . . . . . 345
16.4 Pin description. . . . . . . . . . . . . . . . . . . . . . . . 345
16.5 CAN controller architecture . . . . . . . . . . . . . 345
16.5.1 APB Interface Block (AIB) . . . . . . . . . . . . . . 346
16.5.2 Interface Management Logic (IML). . . . . . . . 346
16.5.3 Transmit Buffers (TXB). . . . . . . . . . . . . . . . . 346
16.5.4 Receive Buffer (RXB) . . . . . . . . . . . . . . . . . 347
16.5.5 Error Management Logic (EML) . . . . . . . . . 348
16.5.6 Bit Timing Logic (BTL) . . . . . . . . . . . . . . . . . 348
16.5.7 Bit Stream Processor (BSP) . . . . . . . . . . . . . 348
16.5.8 CAN controller self-tests. . . . . . . . . . . . . . . . 348
Global self test . . . . . . . . . . . . . . . . . . . . . . . .349
Local self test . . . . . . . . . . . . . . . . . . . . . . . . .349
16.6 Memory map of the CAN block. . . . . . . . . . . 350
16.7 CAN controller registers . . . . . . . . . . . . . . . . 350
16.7.1 CAN Mode register (CAN1MOD - 0x4004 4000,
CAN2MOD - 0x4004 8000) . . . . . . . . . . . . . 352
16.7.2 CAN Command Register (CAN1CMR -
0x4004 x004, CAN2CMR - 0x4004 8004) . . 354
16.7.3 CAN Global Status Register (CAN1GSR -
0x4004 x008, CAN2GSR - 0x4004 8008) . . 355
RX error counter. . . . . . . . . . . . . . . . . . . . . . .357
TX error counter . . . . . . . . . . . . . . . . . . . . . . .357
16.7.4 CAN Interrupt and Capture Register (CAN1ICR -
0x4004 400C, CAN2ICR - 0x4004 800C). . . 358
16.7.5 CAN Interrupt Enable Register (CAN1IER -
0x4004 4010, CAN2IER - 0x4004 8010) . . . 361
16.7.6 CAN Bus Timing Register (CAN1BTR -
0x4004 4014, CAN2BTR - 0x4004 8014). . . 362
Baud rate prescaler . . . . . . . . . . . . . . . . . . . .363
Synchronization jump width . . . . . . . . . . . . . .363
Time segment 1 and time segment 2 . . . . . . .363
16.7.7 CAN Error Warning Limit register (CAN1EWL -
0x4004 4018, CAN2EWL - 0x4004 8018) . . 363
16.7.8 CAN Status Register (CAN1SR - 0x4004 401C,
CAN2SR - 0x4004 801C) . . . . . . . . . . . . . . . 364
16.7.9 CAN Receive Frame Status register (CAN1RFS -
0x4004 4020, CAN2RFS - 0x4004 8020). . . 365
16.7.9.1 ID index field. . . . . . . . . . . . . . . . . . . . . . . . . 366
16.7.10 CAN Receive Identifier register (CAN1RID -
0x4004 4024, CAN2RID - 0x4004 8024) . . . 366
16.7.11 CAN Receive Data register A (CAN1RDA -
0x4004 4028, CAN2RDA - 0x4004 8028) . . 367
16.7.12 CAN Receive Data register B (CAN1RDB -
0x4004 402C, CAN2RDB - 0x4004 802C). . 367
16.7.13 CAN Transmit Frame Information register
(CAN1TFI[1/2/3] - 0x4004 40[30/ 40/50],
CAN2TFI[1/2/3] - 0x4004 80[30/40/50]). . . . 367
Automatic transmit priority detection . . . . . . . 368
Tx DLC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
16.7.14 CAN Transmit Identifier register (CAN1TID[1/2/3]
- 0x4004 40[34/44/54], CAN2TID[1/2/3] -
0x4004 80[34/44/54]). . . . . . . . . . . . . . . . . . 369
16.7.15 CAN Transmit Data register A (CAN1TDA[1/2/3] -
0x4004 40[38/48/58], CAN2TDA[1/2/3] -
0x4004 80[38/48/58]). . . . . . . . . . . . . . . . . . 369
16.7.16 CAN Transmit Data register B (CAN1TDB[1/2/3] -
0x4004 40[3C/4C/5C], CAN2TDB[1/2/3] -
0x4004 80[3C/4C/5C]) . . . . . . . . . . . . . . . . . 370
16.7.17 CAN Sleep Clear register (CANSLEEPCLR -
0x400F C110) . . . . . . . . . . . . . . . . . . . . . . . 370
16.7.18 CAN Wake-up Flags register (CANWAKEFLAGS
- 0x400F C114) . . . . . . . . . . . . . . . . . . . . . . 371
16.8 CAN controller operation . . . . . . . . . . . . . . . 371
16.8.1 Error handling . . . . . . . . . . . . . . . . . . . . . . . 371
16.8.2 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . 371
16.8.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
16.8.4 Transmit priority . . . . . . . . . . . . . . . . . . . . . . 372
16.9 Centralized CAN registers . . . . . . . . . . . . . . 372
16.9.1 Central Transmit Status Register (CANTxSR -
0x4004 0000) . . . . . . . . . . . . . . . . . . . . . . . . 373
16.9.2 Central Receive Status Register (CANRxSR -
0x4004 0004) . . . . . . . . . . . . . . . . . . . . . . . . 373
16.9.3 Central Miscellaneous Status Register (CANMSR
- 0x4004 0008). . . . . . . . . . . . . . . . . . . . . . . 374
16.10 Global acceptance filter . . . . . . . . . . . . . . . . 374
16.11 Acceptance filter modes. . . . . . . . . . . . . . . . 374
16.11.1 Acceptance filter Off mode. . . . . . . . . . . . . . 375
16.11.2 Acceptance filter Bypass mode . . . . . . . . . . 375
16.11.3 Acceptance filter Operating mode . . . . . . . . 375
16.11.4 FullCAN mode . . . . . . . . . . . . . . . . . . . . . . . 375
16.12 Sections of the ID look-up table RAM . . . . . 375
16.13 ID look-up table RAM . . . . . . . . . . . . . . . . . . 376
16.14 Acceptance filter registers. . . . . . . . . . . . . . 378
16.14.1 Acceptance Filter Mode Register (AFMR -
0x4003 C000) . . . . . . . . . . . . . . . . . . . . . . . 378