Because RFL™ and Hubbell® have a policy of continuous product improvement, we reserve the right to change designs and specifications without notice.
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9.2.3.3 PWM CONTROLLER
The duty cycle of the switching element is controlled by the PWM chip (TL494) and associated
components. Modulation of the gate drive is performed by comparison of an internal sawtooth
waveform created by the internal oscillator of U1, with timing components C9 & R11, and either of two
control signals. One signal is provided by an error amplifier for which the feedback voltage is applied to
the non-inverting input through an adjustable voltage divider. The inverting input is connected to a 5V
reference. The output voltage of the amplifier drives the PWM. The duty cycle is inversely proportional
to the amplifier voltage and will adjust the duty cycle to maintain 5V at the non inverting input. The
AC gain of the error amplifier is limited by R9 and C10 to maintain loop stability.
9.2.3.4 FET DRIVE CIRCUIT
Primary current flow is switched by N-Channel FETs Q3 and Q4. Since the gate input of these devices
is highly capacitive, special driving techniques are used to obtain fast switching speeds. Control of the
gate is performed by the PWM controller U1, whose drive outputs are configured as emitter followers.
A Zener regulated supply consisting of CR8, R4, & C11, provides a constant gate voltage and protects
against any overvoltages. During the active portion of each switching cycle, the emitters are pulled up
to the gate voltage supply. To turn off the FET, the energy stored on the gate must be discharged
quickly. This happens when the drive transistors turn off, allowing the base of Q2 to be pulled low
through R13. The FETs are protected from overcurrent by current sense transformer T2, Q7 and
associated components. The gate drive is shut down when the instantaneous current exceeds
approximately 10 amps.
9.2.3.5 SNUBBERS
Flyback power supplies generate very large voltage spikes between power switch turn off and power
rectifier turn on. The transformer used in this design includes a Clamp Winding to control this self
generated voltage spike. The winding is 1:1 with the primary and along with CR12 and C14, limit the
voltage spike to twice the input voltage. The clamped energy is returned to the input filter capacitor C5.
R19 and C12 shape the voltage spike to reduce conducted and radiated EMI.
9.2.3.6 ±15-VOLT OUTPUT CIRCUIT
Since the positive and negative 15V outputs are the same, only the +15V circuitry will be discussed. In
addition it should be mentioned that the -15 volt regulator is powered from an isolated transformer
winding, has a -15 volt ground reference and is output diode clamped to circuit common. The secondary
winding of T1 is rectified by a fast efficient rectifier CR51, and filtered with a low ESR capacitor C51.
This voltage is then applied to the input of the adjustable linear regulator U52. The output voltage of the
regulator is determined by the voltage applied to adjustment input pin #1. Regulation is obtained when
1.275V is present at this pin. The voltage divider R57, R58 & R59, develop this voltage while
compensating for the "ORing" diode voltage drop.
M-DACS-T1 RFL Electronics Inc.
August 7, 2012 9-4 (973) 334-3100
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