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RFL Electronics IMUX 2000 - Figure 3-3. Mapping Block Diagram

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Because RFL and Hubbell® have a policy of continuous product improvement, we reserve the right to change designs and specications without notice.
Source TS ID
MAP & TS ID
(FR_A0 to
FR_A10)
Active Map #
(MAPSEL0 to
MAPSEL2)
Mapped TS ID
(MD1 to MD8)
Tx
TS ID
(QA to QH)
CPU
Dual-Port
RAM
(U11)
Addr
Addr
Addr
Dual-Port
RAM
(U10)
Addr
Actel (U12)
T1
Out T1 In
(RD1 to
RD8)
Rx TS ID
(QA to QH)
TCLK
TSIG
TSYNC
TSER
RSER
RSYNC
RCHCLK
SYSCLK
8 Frame
r
s
“L” “R” “R” “L”
Figure 3-3. Mapping Block Diagram
M-DACS-T1 RFL Electronics Inc.
October 25, 2004 3-7 (973) 334-3100

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