Because RFL™ and Hubbell® have a policy of continuous product improvement, we reserve the right to change designs and specifications without notice.
3.1.2.3.2 RECEIVE DATA
The received data comes into each port (and framer) based upon the timing of the T1 signal. The
DACS has no control over when data will be received. The first task is to gather incoming data and
store it in a useful fashion. This is performed by the mapping Actel (U12). The framer outputs the
received data in a real-time serial data stream (“RSER”). U12 uses the system clock (“SYSCLK”)
coming from the framer, to clock the serial data into a shift-register. The framing sync (“RSYNC”)
and channel clock pulse (“RCHCLK”) signals are used to identify the beginning of frame and timeslot
boundaries, which allow the parallel data to be aligned to match timeslot boundaries and to identify
which timeslot the data comes from.
The Actel then places the data into the “L” side of U10. The eight address lines “QA” through “QH”
are used to select the storage location in U10. There are up to 24 timeslots (in E1), requiring five
address lines (each address stores one byte - one timeslot - of data). There are also eight framers,
requiring three more address lines. Thus the eight address lines.
In a similar fashion, the receive signaling data is captured from the serial data stream provided by the
framer. This data is also converted to parallel, although there are only four signaling bits associated
with each timeslot. Additionally, the signaling data is updated very slowly compared to the payload
data, but the process is much the same. To store this signaling data an additional address line was
added.
Although the signaling data only requires four bits per timeslot, an entire byte of U10 is allocated to
each timeslot. This allows direct re-use of much of the payload receive engine circuitry. This
hardware simplification comes at no cost as the memory still contains four times the amount being
used.
Both the payload and signaling data (after serial-to-parallel conversion) are sent to the “L” side data
lines of U10 (“RD1” through “RD8”).
3.1.2.3.3 TRANSMIT DATA
The transmit process differs from the receive process in two significant ways. The receive circuitry
has no control over the timing of the incoming data, but stores the data in predefined memory
locations. The transmit circuitry generates the timing for the outgoing data but must recall the data
from varying memory locations.
The first step in generating the transmit data stream for a port is to determine which receive timeslot
data is to be transmitted at any particular time. This information is stored in U11. The mapping Actel
U12 specifies which of the eight ports is in question. This requires three bits. U12 must also specify
which timeslot is desired, requiring an additional five bits. This is what constitutes the eight address
lines “QA” through “QH” fed into the “R” side of the map memory U11.
M-DACS-T1 RFL Electronics Inc.
October 25, 2004 3-8 (973) 334-3100
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