Because RFL™ and Hubbell® have a policy of continuous product improvement, we reserve the right to change designs and specifications without notice.
3.1.2.3 DACS MODULE MAPPING FUNCTIONS
A simplified block diagram of the mapping circuitry is shown in Figure 3-3. The receive data from all
eight ports is stored into a dual-port memory (U10) as it arrives. As the data is being transmitted it is
selectively recalled from U10 as required to construct the desired transmit data streams.
The receive functions are independent of the user specified maps - the data is stored into predefined
memory locations. The order in which the data is recalled for transmission is dependent upon the
mapping data. This map data is written into U11 by the processor. All eight maps are written ahead of
time.
During operation, the processor selects which of the eight maps should be used. The mapping Actel
(U12) then reads the required map data from U11 and recalls the appropriate payload data from U10
and sends it to the specified framer.
3.1.2.3.1 MAP DATA
The processor stores the desired map information in dual-port memory U11. The processor has control
over the “L” side port of U11. Three address lines are required to specify one of the eight maps. Three
more address lines are required to specify which the port, and finally, five address lines specify the
particular timeslot (allowing up to 32 for E1 use). This accounts for the eleven address lines
(“FR_A0” through “FR_A10”) fed into U11. These are actual bus address lines from the processor.
For each of the individual timeslots identified, the source of the data to transmit is specified in the map.
This requires three lines to identify the port, and five for the timeslot. This constitutes the byte of
memory.
M-DACS-T1 RFL Electronics Inc.
October 25, 2004 3-6 (973) 334-3100
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