Because RFL™ and Hubbell® have a policy of continuous product improvement, we reserve the right to change designs and specifications without notice.
RFL DS-562I RFL Electronics Inc.
June 14, 2007 26 (973) 334-3100
IMUX 2000 MULTIPLEXER AND RFL 9700 “ORIGINAL” (RS-449)
Interfacing an IMUX 2000 with an RFL 9700 can be accomplished as follows:
A. Configuration of RFL 9700:
97 DIG RX: ECB# 101563: No Clock Polarity Jumper
ECB# 101563-1: J2 - “B” Position
97 DIG TX: No Clock Polarity Jumper
B. The configuration of the IMUX 2000 RS-449 Channel Card shall be as follows:
1. DS-562I with MA-406IA I/O
MA-406IA I/O: J2 jumpers in DCE mode
J3 in any position
DS-562I, Switch SW4-2 (Receive Clock Polarity): ECB #101563: Inverted - OFF (Left)
ECB #101563-1: Normal - ON (Right)
DS-562I, Switch SW4-3 (Transmit Clock Polarity): Normal - ON (Right)
2. DS-562B with MA-406 I/O
MA-406 I/O: No jumpers to set
DS-562B, J1 (Send Timing Clock): Normal - Left (Middle and Front Posts)
DS-562B, J5 (Timing Mode): Internal - UP (Upper and Middle Posts)
NOTE: If the RFL 9700 uses 97 DIG RX having ECB# 101563 (No J2), the signal lines at Tx
Timing “Plus” (Pin 8 of DB-37 Connector) and Rx Timing “Minus” (Pin 26 of DB-37
Connector) must be switched by modifying cable in order to obtain proper RxClock Polarity.
Confirm clock and data transitions before modifying the cable.
C. Confirm Clock and Data Transitions to Insure Proper System Operation as follows:
1. RFL 97 DIG RX: The positive edge of the RxClock (TP2) must be in the center of the
RxData bit (TP1).
2. IMUX 2000: DS-562I - The positive edge of the TxClock (TP3) must be in the center
of the TxData bit (TP1).
DS-562B - The positive edge of the TxClock (U30-Pin 3) must be in the
center of the TxData bit (U30-Pin 2).
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