Sel 421 - Page 30

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SEL-421 Relay Date Code 20090715
List of Figures
Figure 1.45 Phase Instantaneous/Definite-Time Overcurrent Elements...............................................R.1.68
Figure 1.46 Residual Ground Instantaneous/Directional Overcurrent Elements .................................R.1.69
Figure 1.47 Negative-Sequence Instantaneous/Directional Overcurrent Elements..............................R.1.70
Figure 1.48 US Moderately Inverse—U1.............................................................................................R.1.74
Figure 1.49 US Inverse—U2 ................................................................................................................R.1.75
Figure 1.50 US Very Inverse—U3........................................................................................................R.1.76
Figure 1.51 US Extremely Inverse—U4...............................................................................................R.1.77
Figure 1.52 US Short-Time Inverse—U5.............................................................................................R.1.78
Figure 1.53 IEC Standard Inverse—C1................................................................................................R.1.79
Figure 1.54 IEC Very Inverse—C2.......................................................................................................R.1.80
Figure 1.55 IEC Extremely Inverse—C3..............................................................................................R.1.81
Figure 1.56 IEC Long-Time Inverse—C4 ............................................................................................R.1.82
Figure 1.57 IEC Short-Time Inverse—C5............................................................................................R.1.83
Figure 1.58 Selectable Inverse-Time Overcurrent Element Logic Diagram ........................................R.1.84
Figure 1.59 SOTF Logic Diagram........................................................................................................R.1.86
Figure 1.60 Required Zone Directional Settings ..................................................................................R.1.87
Figure 1.61 DCB Logic Diagram .........................................................................................................R.1.91
Figure 1.62 Permissive Trip Receiver Logic Diagram .........................................................................R.1.96
Figure 1.63 POTT Logic Diagram........................................................................................................R.1.97
Figure 1.64 POTT Cross-Country Logic Diagram ...............................................................................R.1.98
Figure 1.65 POTT Scheme Logic (ECOMM := POTT3) With Echo and Weak Infeed.......................R.1.99
Figure 1.66 Permissive Trip Received Logic Diagram.......................................................................R.1.103
Figure 1.67 DCUB Logic Diagram ....................................................................................................R.1.104
Figure 1.68 Trip Logic Diagram.........................................................................................................R.1.112
Figure 1.69 Two Circuit Breakers Trip Logic Diagram......................................................................R.1.114
Figure 1.70 Trip A Unlatch Logic ......................................................................................................R.1.115
Figure 1.71 Trip During Open Pole ....................................................................................................R.1.115
Figure 1.72 Scheme 1 Logic Diagram................................................................................................R.1.116
Figure 1.73 Scheme 2 Three-Pole Circuit Breaker Failure Protection Logic.....................................R.1.117
Figure 1.74 Scheme 2 Single-Pole Circuit Breaker Failure Protection Logic....................................R.1.118
Figure 1.75 Current-Supervised Three-Pole Retrip Logic .................................................................R.1.118
Figure 1.76 Current-Supervised Single-Pole Retrip Logic.................................................................R.1.119
Figure 1.77 No Current/Residual Current Circuit Breaker Failure Protection Logic Diagram..........R.1.119
Figure 1.78 Circuit Breaker Failure Seal-In Logic Diagram ..............................................................R.1.124
Figure 1.79 Failure to Interrupt Load Current Logic Diagram...........................................................R.1.124
Figure 1.80 Flashover Protection Logic Diagram ..............................................................................R.1.125
Figure 1.81 Circuit Breaker Failure Trip Logic Diagram...................................................................R.1.125
Figure 2.1 Auto-Reclose State Diagram for Circuit Breaker 1 ............................................................R.2.4
Figure 2.2 Multiple Circuit Breaker Arrangement .............................................................................R.2.15
Figure 2.3 Multiple Circuit Breaker Arrangement .............................................................................R.2.18
Figure 2.4 Leader/Follower Selection by Relay Input........................................................................R.2.23
Figure 2.5 Circuit Breaker Pole-Open Logic Diagram.......................................................................R.2.27
Figure 2.6 Line-Open Logic Diagram When E79 := Y......................................................................R.2.28
Figure 2.7 Line-Open Logic Diagram When E79 := Y1....................................................................R.2.28
Figure 2.8 Single-Pole Reclose Enable ..............................................................................................R.2.29
Figure 2.9 Three-Pole Reclose Enable ...............................................................................................R.2.29
Figure 2.10 One Circuit Breaker Single-Pole Cycle State (79CY1) ....................................................R.2.30
Figure 2.11 One Circuit Breaker Three-Pole Cycle State (79CY3) .....................................................R.2.31
Figure 2.12 Two Circuit Breakers Single-Pole Cycle State (79CY1) When E79 := Y ........................R.2.32
Figure 2.13 Two Circuit Breakers Single-Pole Cycle State (79CY1) When E79 := Y1 ......................R.2.34
Figure 2.14 Two Circuit Breakers Three-Pole Cycle State (79CY3) When E79 := Y.........................R.2.36
Figure 2.15 Two Circuit Breakers Three-Pole Cycle State (79CY3) When E79 := Y1.......................R.2.39
Figure 2.16 Manual Close Logic ..........................................................................................................R.2.43
Figure 2.17 Voltage Check Element Applications................................................................................R.2.45
Figure 2.18 Voltage Check Element Logic...........................................................................................R.2.46
Figure 2.19 Partial Breaker-and-a-Half or Partial Ring-Bus Breaker Arrangement.............................R.2.51
Figure 2.20 Voltage Angle Difference in a Paralleled System .............................................................R.2.52
Figure 2.21 Synchronism-Check Voltages for Two Circuit Breakers...................................................R.2.52
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