Real-time clock (RTC) RM0453
1028/1454 RM0453 Rev 2
32.6.19 RTC masked interrupt status register (RTC_MISR)
Address offset: 0x54
Backup domain reset value: 0x0000 0000
System reset: not affected
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res.
SSR
UMF
ITS
MF
TSOV
MF
TS
MF
WUT
MF
ALRB
MF
ALRA
MF
rrrrrrr
Bits 31:7 Reserved, must be kept at reset value.
Bit 6 SSRUMF: SSR underflow masked flag
This flag is set by hardware when the SSR underflow interrupt occurs.
Bit 5 ITSMF: Internal timestamp masked flag
This flag is set by hardware when a timestamp on the internal event occurs and
timestampinterrupt is raised.
Bit 4 TSOVMF: Timestamp overflow masked flag
This flag is set by hardware when a timestamp interrupt occurs while TSMF is already set.
It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise,
an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit
is cleared.
Bit 3 TSMF: Timestamp masked flag
This flag is set by hardware when a timestamp interrupt occurs.
If ITSF flag is set, TSF must be cleared together with ITSF.
Bit 2 WUTMF: Wakeup timer masked flag
This flag is set by hardware when the wakeup timer interrupt occurs.
This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1
again.
Bit 1 ALRBMF: Alarm B masked flag
This flag is set by hardware when the alarm B interrupt occurs.
Bit 0 ALRAMF: Alarm A masked flag
This flag is set by hardware when the alarm A interrupt occurs.
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