To Next Page

To Previous Page

RM0453 Rev 2 1029/1454

RM0453 Real-time clock (RTC)

1049

32.6.20 RTC status clear register (RTC_SCR)

Address offset: 0x5C

Backup domain reset value: 0x0000 0000

System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

1514131211109876543210

Res. Res. Res. Res. Res. Res. Res. Res. Res.

CSSR

CITS

CTSOV

CTS

CWUT

CALRB

CALRA

wwwwwww

Bits 31:7 Reserved, must be kept at reset value.

Bit 6 CSSRUF: Clear SSR underflow flag

Writing ‘1’ in this bit clears the SSRUF in the RTC_SR register.

Bit 5 CITSF: Clear internal timestamp flag

Writing 1 in this bit clears the ITSF bit in the RTC_SR register.

Bit 4 CTSOVF: Clear timestamp overflow flag

Writing 1 in this bit clears the TSOVF bit in the RTC_SR register.

It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise,

an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit

is cleared.

Bit 3 CTSF: Clear timestamp flag

Writing 1 in this bit clears the TSOVF bit in the RTC_SR register.

If ITSF flag is set, TSF must be cleared together with ITSF by setting CRSF and CITSF.

Bit 2 CWUTF: Clear wakeup timer flag

Writing 1 in this bit clears the WUTF bit in the RTC_SR register.

Bit 1 CALRBF: Clear alarm B flag

Writing 1 in this bit clears the ALRBF bit in the RTC_SR register.

Bit 0 CALRAF: Clear alarm A flag

Writing 1 in this bit clears the ALRAF bit in the RTC_SR register.

ST STM32WL55JC User Manual

Questions and Answers: