To Next Page

To Previous Page

RM0453 Rev 2 1419/1454

RM0453 Debug support (DBG)

1441

38.12.9 DBGMCU register map and reset values

Bits 31:19 Reserved, must be kept at reset value.

Bit 18 DBG_TIM17_STOP: TIM17 stop in CPU2 debug

0: Normal operation. TIM17 continues to operate while CPU2 is in debug mode.

1: Stop in debug. TIM17 is frozen while CPU2 is in debug mode.

Bit 17 DBG_TIM16_STOP: TIM16 stop in CPU2 debug

0: Normal operation. TIM16 continues to operate while CPU2 is in debug mode.

1: Stop in debug. TIM16 is frozen while CPU2 is in debug mode.

Bits 16:12 Reserved, must be kept at reset value.

Bit 11 DBG_TIM1_STOP: TIM1 stop in CPU2 debug

0: Normal operation. TIM1 continues to operate while CPU2 is in debug mode.

1: Stop in debug. TIM1 is frozen while CPU2 is in debug mode.

Bits 10:0 Reserved, must be kept at reset value.

Table 282. DBGMCU register map and reset values

Offset Register name

0x000

DBGMCU_

IDCODER

REV_ID[15:0]

Res.

DEV_ID[11:0]

Reset value xxxxxxxxxxxxxxxx 010010010111

0x004

DBGMCU_CR

Res.

DBG_STANDBY

DBG_STOP

DBG_SLEEP

Reset value 000

0x008-

0x038

Reserved Reserved.

0x03C

DBGMCU_

APB1FZR1

DBG_LPTIM1_STOP

Res.

DBG_I2C3_STOP

DBG_I2C2_STOP

DBG_I2C1_STOP

Res.

DBG_IWDG_STOP

DBG_WWDG_STOP

DBG_RTC_STOP

Res.

DBG_TIM2_STOP

Reset value 0 000 000 0

0x040

DBGMCU_

C2APB1FZR1

DBG_LPTIM1_STOP

Res.

DBG_I2C3_STOP

DBG_I2C2_STOP

DBG_I2C1_STOP

Res.

DBG_IWDG_STOP

Res.

DBG_RTC_STOP

Res.

DBG_TIM2_STOP

Reset value 0 0 0 0 0 0 0

0x044

DBGMCU_

APB1FZR2

Res.

DBG_LPTIM3_STOP

DBG_LPTIM2_STOP

Res.

Reset value 00

Brand	ST
Model	STM32WL55JC
Category	Microcontrollers
Language	English

ST STM32WL55JC User Manual

Table of Contents

Questions and Answers:

ST STM32WL55JC Specifications

Related product manuals