RM0453 Rev 2 243/1454
RM0453 Power control (PWR)
275
6.5.6 Low-power sleep mode (LPSleep)
Refer to the product datasheet for more details on voltage regulator and peripherals
operating conditions.
I/O states in LPSleep mode
In LPSleep mode, all I/O pins keep the same state as in Run mode.
Enter LPSleep mode
The LPSleep mode is entered from LPRun mode as described in Section 6.5.3: Enter low-
power mode, when the SLEEPDEEP bit in the Cortex system control register is clear.
Refer to Table 50 for details on how to enter the LPSleep mode.
Exit LPSleep mode
The LPSleep mode is exited as described in Section 6.5.4: Exit low-power mode. When
exiting the LPSleep mode by issuing an interrupt or an event, the MCU is in LPRun mode.
Table 49. Sleep mode
Sleep mode Description
Mode entry
WFI (wait for interrupt) or WFE (wait for event) while:
– SLEEPDEEP = 0
– No interrupt (for WFI) or event (for WFE) is pending
Refer to the Cortex system control register.
On return from ISR while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 1
– No interrupt is pending
Refer to the Cortex system control register.
Mode exit
If WFI or return from ISR was used for entry
Interrupt: refer to Table 89: CPU1 vector table, and Table 90: CPU2 vector
table
If WFE was used for entry and SEVONPEND = 0:
Wakeup event: refer to Table 93: Wakeup interrupts
If WFE was used for entry and SEVONPEND = 1:
Interrupt even when disabled in NVIC: refer to Table 89: CPU1 vector table,
and Table 90: CPU2 vector table or wakeup event: refer to Table 93: Wakeup
interrupts
Wakeup latency None
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