Reset and clock control (RCC) RM0453
312/1454 RM0453 Rev 2
7.4.10 RCC AHB3 peripheral reset register (RCC_AHB3RSTR)
Address offset: 0x030
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 GPIOHRST: IO port H reset
This bit is set and cleared by software.
0: No effect
1: IO port H reset
Bits 6:3 Reserved, must be kept at reset value.
Bit 2 GPIOCRST: IO port C reset
This bit is set and cleared by software.
0: No effect
1: IO port C reset
Bit 1 GPIOBRST: IO port B reset
This bit is set and cleared by software.
0: No effect
1: IO port B reset
Bit 0 GPIOARST: IO port A reset
This bit is set and cleared by software.
0: No effect
1: IO port A reset
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res.
FLASH
RST
Res. Res. Res. Res.
IPCC
RST
HSEM
RST
RNG
RST
AES
RST
PKA
RST
rw rw rw rw rw rw
1514131211109 8 76543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Bits 31:26 Reserved, must be kept at reset value.
Bit 25 FLASHRST: Flash interface reset
This bit can only be set when the Flash memory is in power down. It is set and cleared by
software.
0: No effect
1: Flash memory interface reset
Bits 24:21 Reserved, must be kept at reset value.
Bit 20 IPCCRST: IPCC interface reset
This bit is set and cleared by software.
0: No effect
1: IPCC reset
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