RM0453 Rev 2 313/1454
RM0453 Reset and clock control (RCC)
363
7.4.11 RCC APB1 peripheral reset register 1 (RCC_APB1RSTR1)
Address offset: 0x038
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
Bit 19 HSEMRST: HSEM reset
This bit is set and cleared by software.
0: No effect
1: HSEM reset
Bit 18 RNGRST: True RNG reset
This bit is set and cleared by software.
0: No effect
1: True RNG reset
Bit 17 AESRST: AES hardware accelerator reset
This bit is set and cleared by software.
0: No effect
1: AES reset
Bit 16 PKARST: PKA hardware accelerator reset
This bit is set and cleared by software. PKA reset is disabled when a hardware PKA SRAM
erase is ongoing.
0: No effect
1: PKA reset
Bits 15:0 Reserved, must be kept at reset value.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPTIM1
RST
Res.
DAC
RST
Res. Res. Res. Res. Res.
I2C3
RST
I2C2
RST
I2C1
RST
Res. Res. Res.
USART2
RST
Res.
rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res.
SPI2S2
RST
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
TIM2
RST
rw rw
Bit 31 LPTIM1RST: Low-power timer 1 reset
This bit is set and cleared by software.
0: No effect
1: LPTIM1 reset
Bit 30 Reserved, must be kept at reset value.
Bit 29 DACRST: DAC reset
This bit is set and cleared by software.
0: No effect
1: DAC reset
Bits 28:24 Reserved, must be kept at reset value.
To Next Page
Loading...
Need help?
General
