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ST STM32WL55JC User Manual

ST STM32WL55JC
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Reset and clock control (RCC) RM0453
346/1454 RM0453 Rev 2
7.4.38 RCC CPU2 APB2 peripheral clock enable register
(RCC_C2APB2ENR)
Address offset: 0x160
Reset value: 0x0000 0000
Access: word, half-word and byte access
Note: When the peripheral clock is not active, the peripheral registers read or write access from
CPU2 is not supported.
Bit 5 LPTIM2EN: CPU2 low-power timer 2 clocks enable
This bit is set and cleared by software.
0: LPTIM2 bus and kernel clocks disabled for CPU2
1: LPTIM2 bus and kernel clocks enabled for CPU2
Bits 4:1 Reserved, must be kept at reset value.
Bit 0 LPUART1EN: CPU2 low-power UART 1 clocks enable
This bit is set and cleared by software.
0: LPUART1 bus and kernel clocks disabled for CPU2
1: LPUART1 bus and kernel clocks enabled for CPU2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
TIM17
EN
TIM16
EN
Res.
rw rw
1514131211109876543210
Res.
USART1
EN
Res.
SPI1
EN
TIM1
EN
Res.
ADC
EN
Res. Res. Res. Res. Res. Res. Res. Res. Res.
rw rw rw rw
Bits 31:19 Reserved, must be kept at reset value.
Bit 18 TIM17EN: CPU2 timer 17 clock enable
This bit is set and cleared by software.
0: TIM17 clock disabled for CPU2
1: TIM17 clock enabled for CPU2
Bit 17 TIM16EN: CPU2 timer 16 clock enable
This bit is set and cleared by software.
0: TIM16 clock disabled for CPU2
1: TIM16 clock enabled for CPU2
Bits 16:15 Reserved, must be kept at reset value.
Bit 14 USART1EN: CPU2 USART1clocks enable
This bit is set and cleared by software.
0: USART1 bus and kernel clocks disabled for CPU2
1: USART1 bus and kernel clocks enabled for CPU2
Bit 13 Reserved, must be kept at reset value.

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ST STM32WL55JC Specifications

General IconGeneral
BrandST
ModelSTM32WL55JC
CategoryMicrocontrollers
LanguageEnglish

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