RM0453 Rev 2 347/1454
RM0453 Reset and clock control (RCC)
363
7.4.39 RCC CPU2 APB3 peripheral clock enable register
(RCC_C2APB3ENR)
Address offset: 0x164
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
Note: When the peripheral clock is not active, the peripheral registers read or write access from
CPU2 is not supported.
Bit 12 SPI1EN: CPU2 SPI1 clock enable
This bit is set and cleared by software.
0: SPI1 clock disabled for CPU2
1: SPI1 clock enabled for CPU2
Bit 11 TIM1EN: CPU2 timer 1 clock enable
This bit is set and cleared by software.
0: TIM1 clock disabled for CPU2
1: TIM1 clock enabled for CPU2
Bit 10 Reserved, must be kept at reset value.
Bit 9 ADCEN: ADC clocks enable
This bit is set and cleared by software.
0: ADC bus and kernel clocks disabled for CPU2
1: ADC bus and kernel clocks enabled for CPU2
Bits 8:0 Reserved, must be kept at reset value.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
SUBG
HZSPI
EN
rw
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 SUBGHZSPIEN: CPU2 sub-GHz radio SPI clock enable
This bit is set and cleared by software.
0: Sub-GHz radio SPI clock disabled for CPU2
1: Sub-GHz radio SPI clock enabled for CPU2
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