RM0453 Rev 2 373/1454
RM0453 Hardware semaphore (HSEM)
377
8.4.3 HSEM interrupt enable register (HSEM_CnIER)
Address offset: 0x100 + 0x010 * (n - 1), (n = 1 to 2)
Reset value: 0x0000 0000
8.4.4 HSEM interrupt clear register (HSEM_CnICR)
Address offset: 0x104 + 0x010 * (n - 1), (n = 1 to 2)
Reset value: 0x0000 0000
8.4.5 HSEM interrupt status register (HSEM_CnISR)
Address offset: 0x108 + 0x010 * (n - 1), (n = 1 to 2)
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
ISE[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 ISE[15:0]: Interrupt(n) semaphore x enable bit (x = 0 to 15)
This bit is read and written by software.
0: Interrupt(n) generation for semaphore x disabled (masked)
1: Interrupt(n) generation for semaphore x enabled (not masked)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
ISC[15:0]
rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 ISC[15:0]: Interrupt(n) semaphore x clear bit (x = 0 to 15)
This bit is written by software, and is always read 0.
0: Interrupt(n) semaphore x status ISFx and masked status MISFx not affected.
1: Interrupt(n) semaphore x status ISFx and masked status MISFx cleared.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
ISF[15:0]
rrrrrrrrrrrrrrrr
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