RM0453 Rev 2 387/1454
RM0453 Inter-processor communication controller (IPCC)
391
9.4.3 IPCC processor 1 status set clear register (IPCC_C1SCR)
Address offset: 0x008
Reset value: 0x0000 0000
Reading this register always returns 0x0000 0000.
9.4.4 IPCC processor 1 to processor 2 status register
(IPCC_C1TOC2SR)
Address offset: 0x00C
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CH6S CH5S CH4S CH3S CH2S CH1S
rw rw rw rw rw rw
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CH6C CH5C CH4C CH3C CH2C CH1C
rw rw rw rw rw rw
Bits 31:22 Reserved, must be kept at reset value.
Bits 21:16 CHnS: Processor 1 transmit channel n status set (n = 6 to 1).
Associated with IPCC_C1TOC2SR.CHnF
1: Processor 1 transmit channel n status bit set.
0: No action.
Bits 15:6 Reserved, must be kept at reset value.
Bits 5:0 CHnC: Processor 1 receive channel n status clear (n = 6 to 1).
Associated with IPCC_C2TOC1SR.CHnF
1: Processor 1 receive channel n status bit clear.
0: No action.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CH6F CH5F CH4F CH3F CH2F CH1F
rrrrrr
Bits 31:6 Reserved, must be kept at reset value.
Bits 5:0 CHnF: Processor 1 transmit to processor 2 receive channel n status flag before masking (n = 6
to 1).
1: Channel occupied, data can be read by the receiving processor 2.
Generates a channel RX occupied interrupt to processor 2, when unmasked.
0: Channel free, data can be written by the sending processor 1.
Generates a channel TX free interrupt to processor 1, when unmasked.
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