RM0453 Rev 2 419/1454
RM0453 General-purpose I/Os (GPIO)
426
10.4.27 GPIOH input data register (GPIOH_IDR)
Address offset: 0x1C10
Reset value: 0x0000 000X
10.4.28 GPIOH output data register (GPIOH_ODR)
Address offset: 0x1C14
Reset value: 0x0000 0000
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:6 PUPD3[1:0]: Port PH3 pull configuration
These bits are written by software to configure the I/O pull-up or pull-down.
00: No pull-up, pull-down
01: Pull-up
10: Pull-down
11: Reserved
Bits 5:0 Reserved, must be kept at reset value.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ID3 Res. Res. Res.
r
Bits 31:4 Reserved, must be kept at reset value.
Bit 3 ID3: Port PH3 input data bit
This bit is read-only. It contains the input value of the corresponding I/O port.
Bits 2:0 Reserved, must be kept at reset value.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OD3 Res. Res. Res.
rw
Bits 31:4 Reserved, must be kept at reset value.
Bit 3 OD3: Port PH3 output data
This bit can be read and written by software.
Note: For atomic bit set/reset, OD bits can be individually set and/or reset by writing to the
GPIOH_BSRR and GPIOH_BRR registers.
Bits 2:0 Reserved, must be kept at reset value.
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