System configuration controller (SYSCFG) RM0453
434/1454 RM0453 Rev 2
Note: Some of the I/O pins mentioned in this register may not be available on small packages.
11.2.7 SYSCFG SRAM control and status register (SYSCFG_SCSR)
Address offset: 0x18
Reset value: 0x0000 0000
Bits 6:4 EXTI13[2:0]: EXTI13 configuration bits
These bits are written by software to select the source input for the EXTI13 external interrupt.
000: PA13 pin
001: PB13 pin
010: PC13 pin
011: Reserved
100: Reserved
101: Reserved
110: Reserved
111: Reserved
Bit 3 Reserved, must be kept at reset value.
Bits 2:0 EXTI12[2:0]: EXTI12 configuration bits
These bits are written by software to select the source input for the EXTI12 external interrupt.
000: PA12 pin
001: PB12 pin
010: Reserved
011: Reserved
100: Reserved
101: Reserved
110: Reserved
111: Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res.
PKASRAMBSY
Res. Res. Res. Res. Res. Res.
SRAMBSY
SRAM2ER
rrrw
Bits 31:9 Reserved, must be kept at reset value.
Bit 8 PKASRAMBSY: PKA SRAM busy by erase operation
0: No PKA SRAM erase operation is ongoing.
1: PKA SRAM erase operation is ongoing.
See Section 2.4: SRAM erase for more information on SRAM erase conditions
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